Patents by Inventor Robert SPIVEY
Robert SPIVEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12474537Abstract: Technologies for an optomechanical system include an intermediate plate having a top surface with multiple tapped holes arranged in a grid. A pair of dowel pin holes surround each tapped hole in a linear pattern. Multiple optical blocks are coupled to the intermediate plate using dowel pins positioned in the dowel pin holes and corresponding dowel pin holes defined in the bottom surface of the optical block. Each optical block includes multiple optical elements coupled to the top surface of the optical block with dowel pins. A cryostat may be coupled to the intermediate plate. A cryo-package assembly is mounted inside a cryo chamber of the cryostat. The cryo-package assembly includes a cryo device such as an ion trap covered by a machined copper lid. The lid includes a meandering passageway to allow for differential pumping in order to achieve ultra-high vacuum within the cryo-package assembly.Type: GrantFiled: August 8, 2022Date of Patent: November 18, 2025Assignee: Duke UniversityInventors: Jungsang Kim, Ismail Inlek, Robert Spivey
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Patent number: 12142473Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.Type: GrantFiled: July 18, 2023Date of Patent: November 12, 2024Assignee: Duke UniversityInventors: Jungsang Kim, Kai Hudek, Geert Vrijsen, Robert Spivey, Peter Maunz
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Publication number: 20240162028Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.Type: ApplicationFiled: July 18, 2023Publication date: May 16, 2024Inventors: Jungsang KIM, Kai HUDEK, Geert VRIJSEN, Robert SPIVEY, Peter MAUNZ
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Patent number: 11749518Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.Type: GrantFiled: June 26, 2020Date of Patent: September 5, 2023Assignee: Duke UniversityInventors: Jungsang Kim, Kai Hudek, Geert Vrijsen, Robert Spivey, Peter Maunz
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Publication number: 20230037882Abstract: Technologies for an optomechanical system include an intermediate plate having a top surface with multiple tapped holes arranged in a grid. A pair of dowel pin holes surround each tapped hole in a linear pattern. Multiple optical blocks are coupled to the intermediate plate using dowel pins positioned in the dowel pin holes and corresponding dowel pin holes defined in the bottom surface of the optical block. Each optical block includes multiple optical elements coupled to the top surface of the optical block with dowel pins. A cryostat may be coupled to the intermediate plate. A cryo-package assembly is mounted inside a cryo chamber of the cryostat. The cryo-package assembly includes a cryo device such as an ion trap covered by a machined copper lid. The lid includes a meandering passageway to allow for differential pumping in order to achieve ultra-high vacuum within the cryo-package assembly.Type: ApplicationFiled: August 8, 2022Publication date: February 9, 2023Inventors: Robert Spivey, Kai Hedek, Ismail Inlek, Jungsang Kim, Zhubing Jia
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Patent number: 11538674Abstract: Systems and methods for loading microfabricated ion traps are disclosed. Photo-ablation via an ablation pulse is used to generate a flow of atoms from a source material, where the flow is predominantly populated with neutral atoms. As the neutral atoms flow toward the ion trap, two-photon photo-ionization is used to selectively ionize a specific isotope contained in the atom flow. The velocity of the liberated atoms, atom-generation rate, and/or heat load of the source material is controlled by controlling the fluence of the ablation pulse to provide high ion-trapping probability while simultaneously mitigating generation of heat in the ion-trapping system that can preclude cryogenic operation. In some embodiments, the source material is held within an ablation oven comprising an electrically conductive housing that is configured to restrict the flow of agglomerated neutral atoms generated during photo-ablation toward the ion trap.Type: GrantFiled: November 17, 2020Date of Patent: December 27, 2022Assignee: Duke UniversityInventors: Geert Vrijsen, Jungsang Kim, Robert Spivey, Ismail Inlek, Yuhi Aikyo
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Publication number: 20210217598Abstract: Systems and methods for loading microfabricated ion traps are disclosed. Photo-ablation via an ablation pulse is used to generate a flow of atoms from a source material, where the flow is predominantly populated with neutral atoms. As the neutral atoms flow toward the ion trap, two-photon photo-ionization is used to selectively ionize a specific isotope contained in the atom flow. The velocity of the liberated atoms, atom-generation rate, and/or heat load of the source material is controlled by controlling the fluence of the ablation pulse to provide high ion-trapping probability while simultaneously mitigating generation of heat in the ion-trapping system that can preclude cryogenic operation. In some embodiments, the source material is held within an ablation oven comprising an electrically conductive housing that is configured to restrict the flow of agglomerated neutral atoms generated during photo-ablation toward the ion trap.Type: ApplicationFiled: November 17, 2020Publication date: July 15, 2021Inventors: Geert VRIJSEN, Jungsang KIM, Robert SPIVEY, Ismail INLEK, Yuhi AIKYO
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Patent number: 10923335Abstract: Systems and methods for loading microfabricated ion traps are disclosed. Photo-ablation via an ablation pulse is used to generate a flow of atoms from a source material, where the flow is predominantly populated with neutral atoms. As the neutral atoms flow toward the ion trap, two-photon photo-ionization is used to selectively ionize a specific isotope contained in the atom flow. The velocity of the liberated atoms, atom-generation rate, and/or heat load of the source material is controlled by controlling the fluence of the ablation pulse to provide high ion-trapping probability while simultaneously mitigating generation of heat in the ion-trapping system that can preclude cryogenic operation. In some embodiments, the source material is held within an ablation oven comprising an electrically conductive housing that is configured to restrict the flow of agglomerated neutral atoms generated during photo-ablation toward the ion trap.Type: GrantFiled: March 19, 2019Date of Patent: February 16, 2021Assignee: Duke UniversityInventors: Geert Vrijsen, Jungsang Kim, Robert Spivey, Ismail Inlek, Yuhi Aikyo
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Publication number: 20200335320Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.Type: ApplicationFiled: June 26, 2020Publication date: October 22, 2020Inventors: Jungsang KIM, Kai HUDEK, Geert VRIJSEN, Robert SPIVEY, Peter MAUNZ
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Patent number: 10755913Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.Type: GrantFiled: March 26, 2018Date of Patent: August 25, 2020Assignee: Duke UniversityInventors: Jungsang Kim, Kai Hudek, Geert Vrijsen, Robert Spivey, Peter Maunz
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Patent number: 10496932Abstract: Aspects of the present disclosure describe a compact RF driver circuit for Paul traps in trapped ion quantum computers and methods, and structures including same.Type: GrantFiled: July 18, 2018Date of Patent: December 3, 2019Assignee: Duke UniversityInventors: Jungsang Kim, Geert Vrijsen, Robert Spivey
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Publication number: 20190287782Abstract: Systems and methods for loading microfabricated ion traps are disclosed. Photo-ablation via an ablation pulse is used to generate a flow of atoms from a source material, where the flow is predominantly populated with neutral atoms. As the neutral atoms flow toward the ion trap, two-photon photo-ionization is used to selectively ionize a specific isotope contained in the atom flow. The velocity of the liberated atoms, atom-generation rate, and/or heat load of the source material is controlled by controlling the fluence of the ablation pulse to provide high ion-trapping probability while simultaneously mitigating generation of heat in the ion-trapping system that can preclude cryogenic operation. In some embodiments, the source material is held within an ablation oven comprising an electrically conductive housing that is configured to restrict the flow of agglomerated neutral atoms generated during photo-ablation toward the ion trap.Type: ApplicationFiled: March 19, 2019Publication date: September 19, 2019Inventors: Geert VRIJSEN, Jungsang KIM, Robert SPIVEY, Ismail INLEK, Yuhi AIKYO
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Publication number: 20190057318Abstract: Aspects of the present disclosure describe a compact RF driver circuit for Paul traps in trapped ion quantum computers and methods, and structures including same.Type: ApplicationFiled: July 18, 2018Publication date: February 21, 2019Inventors: Jungsang KIM, Geert VRIJSEN, Robert SPIVEY
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Publication number: 20190027355Abstract: A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.Type: ApplicationFiled: March 26, 2018Publication date: January 24, 2019Inventors: Jungsang KIM, Kai HUDEK, Geert VRIJSEN, Robert SPIVEY, Peter MAUNZ