Patents by Inventor Robert Staszewski

Robert Staszewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200007134
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 10079608
    Abstract: Time-to-digital converter system including: an event detector configured for detecting an event and generating an event detection signal upon detection of the event; and a time-to-digital converter coupled or connectable to the event detector and including a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager including an array of pixels, with in each pixel such a time-to-digital converter system, and further including a reference clock generator.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: September 18, 2018
    Assignee: FASTREE 3D BV
    Inventors: Priyanka Kumar, Robert Staszewski, Edoardo Charbon
  • Patent number: 9419635
    Abstract: 3D imager including at least one pixel, each pixel including a photodetector for detecting photon incidence and a time-to-digital converter system configured for referencing the photon incidence to a reference clock, and further including a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: August 16, 2016
    Assignee: FASTREE 3D BV
    Inventors: Priyanka Kumar, Robert Staszewski, Edoardo Charbon
  • Publication number: 20140232827
    Abstract: Time-to-digital converter system including: an event detector configured for detecting an event and generating an event detection signal upon detection of the event; and a time-to-digital converter coupled or connectable to the event detector and including a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager including an array of pixels, with in each pixel such a time-to-digital converter system, and further including a reference clock generator.
    Type: Application
    Filed: September 10, 2012
    Publication date: August 21, 2014
    Applicant: FASTREE 3D BV
    Inventors: Priyanka Kumar, Robert Staszewski, Edoardo Charbon
  • Publication number: 20140226166
    Abstract: 3D imager including at least one pixel, each pixel including a photodetector for detecting photon incidence and a time-to-digital converter system configured for referencing the photon incidence to a reference clock, and further including a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence.
    Type: Application
    Filed: September 10, 2012
    Publication date: August 14, 2014
    Applicant: Fastree 3D BV
    Inventors: Priyanka Kumar, Robert Staszewski, Edoardo Charbon
  • Patent number: 7623838
    Abstract: A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: November 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Staszewski, Khurram Muhammad, Yo-Chuol Ho, Dirk Leipold
  • Publication number: 20080061892
    Abstract: A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the oscillator circuit tank circuit. The system further includes a synchronizer coupled to the single-electron device and configured to cause the single-electron device to inject the single electron into the resonant tank circuit at a phase based on an extreme (maximum or minimum) electrical characteristic output of the resonant tank circuit.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 13, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Robert Staszewski, Renaldi Winoto, Dirk Leipold
  • Publication number: 20080054253
    Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Robert Staszewski, Renaldi Winoto, Dirk Leipold
  • Publication number: 20080057878
    Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Robert Staszewski, Renaldi Winoto, Dirk Leipold
  • Publication number: 20080043818
    Abstract: A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency.
    Type: Application
    Filed: September 18, 2007
    Publication date: February 21, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nir Tal, Robert Staszewski, Ofer Friedman
  • Publication number: 20080002788
    Abstract: A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited modulation range to handle the large modulation ranges demanded by modern wideband wireless standards such as 3G WCDMA, etc. A controllable oscillator generates an RF signal having four quadrature phases in accordance with an input command signal. An exception handler compares the frequency command information against a threshold. If it exceeds the threshold a phase jump and a residue frequency command are generated. The residue frequency command is input to an oscillator which is operative to generate an RF signal having four quadrature phases. The phase jump is input to a quadrature switch which functions to select one of the four quadrature phase signals as the output RF signal which is then fed to a digital power amplifier.
    Type: Application
    Filed: September 10, 2007
    Publication date: January 3, 2008
    Inventors: Siraj Akhtar, Mehmet Ipek, Robert Staszewski
  • Publication number: 20070182496
    Abstract: A novel testing mechanism operative to test large capacitor arrays such as those used in a digitally controlled crystal oscillator (DCXO). The invention is adapted for use in DCXO circuits that employ dynamic element matching in their array decoding circuits. The invention combines the use of DEM during regular operation of the DCXO with a testing technique that greatly reduces the number of tests required. The invention tests the capacitors in the array on a row by row, wherein all the capacitors in a row are tested lumped together and treated as a single entity, which results in significantly reduced testing time.
    Type: Application
    Filed: October 19, 2006
    Publication date: August 9, 2007
    Inventors: John Wallberg, Robert Staszewski, Vanessa Bodrero
  • Publication number: 20070110194
    Abstract: A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.
    Type: Application
    Filed: October 19, 2006
    Publication date: May 17, 2007
    Inventors: Elida de Obaldia, Robert Staszewski, Dirk Leipold
  • Publication number: 20070103240
    Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
    Type: Application
    Filed: January 3, 2007
    Publication date: May 10, 2007
    Inventors: Robert Staszewski, Gennady Feygin, Oren Eliezer, Dirk Leipold
  • Publication number: 20070085579
    Abstract: A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 19, 2007
    Inventors: John Wallberg, Robert Staszewski
  • Publication number: 20070085621
    Abstract: A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop (ADPLL). The acquisition bits of the acquisition bank are used as an extension of the modulation range. The PLL and TX tuning data are broken up (i.e. apportioned) into acquisition components and tracking components. This permits the use of two different capacitor banks (i.e. the tracking and acquisition banks) for modulation rather than just a single capacitor bank as in the prior art schemes. Incorporating the tracking and acquisition bit varactors, the cooperation scheme of the present invention permits the re-centering of the tracking bank to handle natural frequency drift of the DCO and the widening of the modulation range.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 19, 2007
    Inventors: Robert Staszewski, John Wallberg
  • Publication number: 20070085622
    Abstract: A novel gear shifting mechanism operative to adjust the loop gain of a phase locked loop (PLL) circuit in a continuous and reversible manner. The loop gain can be increased to widen the bandwidth of the loop and can also be decreased to narrow the loop bandwidth. The mechanism incorporates an ? gear shift circuit, a p gear shift circuit and an optional IIR gear shift circuit. The ? gear shift circuit comprises a infinite impulse response (IIR) filtering which enables hitless operation of the PLL loop at the occurrence of gear shift events. The ? gear shift circuit comprises an accumulator whose output is multiplied by the gain value ?. The invention enables multiple gear shifts in either positive or negative direction to be achieved by configuring the loop gain variables ? and ? which may be accomplished in software.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 19, 2007
    Inventors: John Wallberg, Robert Staszewski
  • Publication number: 20070085623
    Abstract: A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 19, 2007
    Inventors: Robert Staszewski, John Wallberg
  • Publication number: 20070008199
    Abstract: A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
    Type: Application
    Filed: July 11, 2005
    Publication date: January 11, 2007
    Inventors: Sameh Rezeq, Dirk Leipold, Robert Staszewski, Chih-Ming Hung
  • Publication number: 20060291589
    Abstract: A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, ?). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.
    Type: Application
    Filed: August 11, 2005
    Publication date: December 28, 2006
    Inventors: Oren Eliezer, Francis Cruise, Robert Staszewski, Jaimin Mehta