Patents by Inventor Robert Stenberg

Robert Stenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for identifying and eliminating bottlenecks in integrated circuit designs
    Patent number: 6757877
    Abstract: A method of integrated circuit design and a circuit design tool. Critical paths are identified in an integrated circuit design. Identified edges are weighted. Edges are assigned a higher weight responsive to the number of critical paths in which they are included. A net criticality is assigned to each weighted edge based upon the edge's weight. Cells are re-placed and wired according to net criticality.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: June 29, 2004
    Assignee: LSI Logic Corporation
    Inventors: Robert Stenberg, Ivan Pavisic
  • System and method for identifying and eliminating bottlenecks in integrated circuit designs
    Publication number: 20030163797
    Abstract: A method of integrated circuit design and a circuit design tool. Critical paths are identified in an integrated circuit design. Identified edges are weighted. Edges are assigned a higher weight responsive to the number of critical paths in which they are included. A net criticality is assigned to each weighted edge based upon the edge's weight. Cells are re-placed and wired according to net criticality.
    Type: Application
    Filed: February 27, 2002
    Publication date: August 28, 2003
    Applicant: LSI LOGIC CORPORATION
    Inventors: Robert Stenberg, Ivan Pavisic