Abstract: A radio communications device 100 including a processor 120 having a digital signal processor (DSP) coupled to a transceiver 110. The transceiver includes a digital-to-phase synthesizer having one or more independently variable frequency or phase signal outputs coupled to a transmitter and/or to a receiver. The variable frequency and phase outputs of the digital-to phase synthesizer are mixed with corresponding received signals and are capable of frequency or phase modulating information signals for transmission. Amplitude modulated signals may be provided through polar modulation by combining synthesizer outputs at a summer.

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract: A vector signal processor (80) can include a digital to time converter (DTC), an RF memory (RFM) or an electronically tunable transmission line (ETTL) (82), a mixer, or other phase shifter (70) for receiving an output of the DTC or the ETTL, and a controller for selectively controlling the harmonic processing of the DTC, RFM or the ETTL and the phase processing of the mixer. The vector signal processor can uncouple a relative phase of a fundamental signal with respect to harmonics of the fundamental signal. The vector signal processor uses selective phase processing of the fundamental signal and related harmonic components. In a specific embodiment, the vector signal processor cancels harmonics of the fundamental signal and more specifically can cancel a third harmonic of the fundamental signal.

Abstract: A direct digital synthesizer (30) with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer (40) and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter (44) and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal (49) to the quantizer and an output signal (43) from the quantizer. The ROM-less direct digital synthesizer can further include a dither (39) combined at an input of the quantizer.

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract: A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).

Abstract: A dynamically matched mixer system (200) for use in a direct conversion radio frequency (RF) receiver includes a frequency generator (201, 203, 205) that includes plurality of dividers (407) for providing differential local oscillator reference sources (FLO+ and FLO?) and mitigation frequency reference sources (F1 and F2) from reference oscillator (205). A mixer (209) mixes the differential local oscillator reference sources (FLO+ and FLO?) and the mitigation frequency reference sources (F1 and F2) while dynamic matching units (211, 213) are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (IRF+ and IRF?) and differential baseband output signals (IBB+ and IBB?).

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Abstract: A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18, . . . , 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A frequency generator (10) includes a direct digital synthesizer (14) having an accumulator (18 or 28) for providing an interim output and a digital interpolator (16) for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter (22) or a digital-to-time converter (32). The frequency generator can further include a digitally programmable spreading function (12) applied to an input of the direct digital synthesizer.

Abstract: A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A direct digital synthesizer (30) with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer (40) and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter (44) and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal (49) to the quantizer and an output signal (43) from the quantizer. The ROM-less direct digital synthesizer can further include a dither (39) combined at an input of the quantizer.

Abstract: A frequency generator (10) includes a direct digital synthesizer (14) having an accumulator (18 or 28) for providing an interim output and a digital interpolator (16) for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter (22) or a digital-to-time converter (32). The frequency generator can further include a digitally programmable spreading function (12) applied to an input of the direct digital synthesizer.

Abstract: A radio communications device 100 including a processor 120 having a digital signal processor (DSP) coupled to a transceiver 110. The transceiver includes a digital-to-phase synthesizer having one or more independently variable frequency or phase signal outputs coupled to a transmitter and/or to a receiver. The variable frequency and phase outputs of the digital-to phase synthesizer are mixed with corresponding received signals and are capable of frequency or phase modulating information signals for transmission. Amplitude modulated signals may be provided through polar modulation by combining synthesizer outputs at a summer.

Abstract: A distributed amplifier consistent with certain embodiments of the present invention has a plurality of amplifier sections 1 through N (302, 306) with each amplifier section having an input and an output. A plurality of N input transmission line sections are connected in series, with inputs of the 1 through N amplifier sections interconnected at their inputs along the series of input transmission line sections. A plurality of N output transmission line sections are also connected in series, with outputs of the 1 through N amplifier sections interconnected at their outputs along the series of input transmission line sections. A load (160) can be driven by an output at the Nth amplifier section (108). A high-pass filter (310) connects a dummy load (150) to the output of the first amplifier section (302). The input and output transmission line sections can, for example, be lumped element T sections and the high-pass filter can be made of a lumped element half section.

Abstract: A high efficiency amplifier arrangement consistent with certain embodiments of the invention has an amplifier (104) that receives an input signal and amplifies the input signal to produce an output signal that drives a load (108). A variable impedance transformer (300) is disposed between the amplifier (104) and the load (108) to presents a varying load impedance to the output of the amplifier (104). A control mechanism, such as a programmed processor (604, 504), controls the variable impedance transformer (300) with a control signal so that the load impedance seen by the amplifier (104) varies in accordance with an envelope of the input signal. The control signal varies the load impedance in a manner that keeps the output of the amplifier (104) near a peak value. The arrangement may further include a circuit for controlling a DC input bias (420) of the amplifier (104) to keep the amplifier (104) operating within a predetermined class of operation throughout a range of input signals.

Abstract: A distributed amplifier arrangement (300) is provided in which a plurality of input signals (S1(t), . . . SN(t)) are separately controlled by a drive generator circuit (315) to produce modulation of a virtual load impedance at each amplifier stage. This permits each stage (302, 304, . . . 310) of the distributed amplifier (300) to operate at maximum efficiency by permitting the stage to produce an output voltage that approaches the supply voltage. As the output power is reduced, efficiency is maintained by systematically reducing the number of stages contributing to the output to the load.

Abstract: A frequency selective differential amplifier (400) consistent with certain embodiments of the invention has a plurality of N amplifier stages (401, 402, 403 through 404) that collectively drive load (410). The plurality of N amplifier stages (401, 402, 403, . . . , 404) have input nodes and output nodes. A plurality of N−1 output phase shift circuits (421, 422, . . . , 423) connect the output nodes of the plurality of amplifier stages in a manner that causes output signals from the plurality of output nodes to add together for delivery to the load (410), the plurality of output phase shift circuits (421, 422, . . . , 423) have a plurality of phase shifts of &thgr;(f)={&thgr;(f)1,2; &thgr;(f)2,3; . . . ; &thgr;(f)N−2,N−1}. A plurality of N−1 input phase shift circuits (431, 432 through 433) are coupled to the plurality of input nodes and provide input signals thereto. The plurality of input phase shift circuits (431, 432, . . .

Abstract: A frequency selective differential amplifier (400) consistent with certain embodiments of the invention has a plurality of N amplifier stages (401, 402, 403 through 404) that collectively drive load (410). The plurality of N amplifier stages (401, 402, 403, . . . , 404) have input nodes and output nodes. A plurality of N−1 output phase shift circuits (421, 422, . . . , 423) connect the output nodes of the plurality of amplifier stages in a manner that causes output signals from the plurality of output nodes to add together for delivery to the load (410), the plurality of output phase shift circuits (421, 422, . . . , 423) have a plurality of phase shifts of &thgr;(f)={&thgr;(f)1,2; &thgr;(f)2,3; . . . ; &thgr;(f)N−2,N−1}. A plurality of N−1 input phase shift circuits (431, 432 through 433) are coupled to the plurality of input nodes and provide input signals thereto. The plurality of input phase shift circuits (431, 432, . . .