Patents by Inventor Robert Stephenson

Robert Stephenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070225463
    Abstract: Organic substrates such as grain by-products: wet cake, mash, stillage, wet brewers cake are dewatered in a relatively low energy, low-heated gas flow, negative pressure, four stage process consisting of leaching with organic solvent, mechanical dewatering, evaporation and reclamation of the organic solvent in an environment of a stable gas flow. The dried organic substrate is processed into a dry distiller's grains with solubles which is free-flowing quality substance suitable for food or other uses at much lower substrate drying temperatures generally below 200° F. Conveniently, the solvent and the stable gases are recovered from the water-solvent leaching and dewatering process by a distillation tower and feedback loop system allowing the recycling of the solvent and stable gas while reducing the level of air emissions in the unique drying system.
    Type: Application
    Filed: March 27, 2006
    Publication date: September 27, 2007
    Inventors: Michael Femal, Robert Stephenson, Frederick Tegge, David Stringham, David Schwerbel, Jon Kellett
  • Publication number: 20070197006
    Abstract: A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. More particularly, the superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. Furthermore, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 23, 2007
    Applicant: RJ Mears, LLC
    Inventors: Ilija Dukovski, Robert Stephenson, Jean Augustin Chan Yiptong, Samed Halilov, Robert Mears, Xiangyang Huang, Marek Hytha
  • Publication number: 20070194298
    Abstract: A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The device may also include a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. The superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 23, 2007
    Applicant: RJ Mears, LLC
    Inventors: Ilija Dukovski, Robert Stephenson, Jean Augustin Yiptong, Samed Halilov, Robert Mears, Xiangyang Huang, Marek Hytha
  • Publication number: 20070187667
    Abstract: An electronic device may include a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The electronic device may also include at least one electrode for selectively poling the selectively polable superlattice.
    Type: Application
    Filed: December 21, 2006
    Publication date: August 16, 2007
    Applicant: RJ Mears, LLC
    Inventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Chan Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
  • Publication number: 20070166928
    Abstract: A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof.
    Type: Application
    Filed: December 21, 2006
    Publication date: July 19, 2007
    Applicant: RJ Mears, LLC
    Inventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
  • Publication number: 20070158640
    Abstract: An electronic device may include a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The electronic device may further include at least one electrode coupled to the poled superlattice.
    Type: Application
    Filed: December 21, 2006
    Publication date: July 12, 2007
    Applicant: RJ Mears, LLC
    Inventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
  • Publication number: 20070161138
    Abstract: A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the poled superlattice.
    Type: Application
    Filed: December 21, 2006
    Publication date: July 12, 2007
    Applicant: RJ Mears, LLC
    Inventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
  • Patent number: 7210727
    Abstract: A roof bow adapted to support a roof skin of a trailer and be affixed to spaced apart top rails of the trailer. The roof bow includes an elongated channel and a pair of end pieces affixed to opposite ends of the elongated channel by clinching. When viewed in cross section transverse to its general extent, the channel includes a substantially flat central portion and extending end portions defining support surfaces offset vertically from the central portion. The support surfaces are adapted to support the trailer sheet skin. Each end piece includes a substantially flat flange and an angled arm extending away from the flange. The angled arm adapted to be affixed to a respective one of the trailer top rails. For each of the pair of end pieces, a plurality of clinch joints affix the flange to the central portion of the channel.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: May 1, 2007
    Assignee: The Ohio Moulding Corporation
    Inventors: Robert A. Stephenson, Chad M. England, John C. Lokotar
  • Publication number: 20070072817
    Abstract: The present invention relates to methods and agents for reducing blood pressure. Methods and agents for reducing diastolic blood pressure, for reducing systolic blood pressure, and for reducing mean arterial pressure are also provided.
    Type: Application
    Filed: May 5, 2006
    Publication date: March 29, 2007
    Applicant: FibroGen, Inc.
    Inventors: Ingrid Langsetmo Parobok, Todd Seeley, Robert Stephenson
  • Publication number: 20060273299
    Abstract: A method for making a semiconductor device may include forming at least one metal oxide field-effect transistor (MOSFET) by forming a body, forming a dopant blocking superlattice adjacent the body, and forming a channel layer adjacent the dopant blocking superlattice and opposite the body. The dopant blocking superlattice may include a plurality of stacked groups of layers. Each group of layers of the dopant blocking superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: May 1, 2006
    Publication date: December 7, 2006
    Applicant: RJ Mears, LLC
    Inventors: Robert Stephenson, Marek Hytha
  • Publication number: 20060249977
    Abstract: A roof bow adapted to support a roof skin of a trailer and be affixed to spaced apart top rails of the trailer. The roof bow includes an elongated channel and a pair of end pieces affixed to opposite ends of the elongated channel by clinching. When viewed in cross section transverse to its general extent, the channel includes a substantially flat central portion and extending end portions defining support surfaces offset vertically from the central portion. The support surfaces are adapted to support the trailer sheet skin. Each end piece includes a substantially flat flange and an angled arm extending away from the flange. The angled arm adapted to be affixed to a respective one of the trailer top rails. For each of the pair of end pieces, a plurality of clinch joints affix the flange to the central portion of the channel.
    Type: Application
    Filed: May 6, 2005
    Publication date: November 9, 2006
    Inventors: Robert Stephenson, Chad England, John Lokotar
  • Publication number: 20060220118
    Abstract: A semiconductor device may include at least one metal oxide field-effect transistor (MOSFET). The at least one MOSFET may include a body, a channel layer adjacent the body, and a dopant blocking superlattice between the body and the channel layer. The dopant blocking superlattice may include a plurality of stacked groups of layers. Each group of layers of the dopant blocking superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: May 1, 2006
    Publication date: October 5, 2006
    Applicant: RJ Mears, LLC
    Inventors: Robert Stephenson, Marek Hytha
  • Publication number: 20060022800
    Abstract: A system and method of scheduling RFID tag interrogations by a plurality of RFID readers so as to mitigate the effects of interference within an RFID environment in which the readers are deployed, and to enhance the efficiency and reliability of the overall RFID system. The system includes a plurality of RFID receivers for receiving RFID tag data, a plurality of RFID tag interrogators for transmitting RF interrogation signals for interrogating RFID tags, and a controller for providing to at least one interrogator, at least one receiver, and at least one tag, a parameter associated with operational characteristics of the interrogator, the receiver, and the tag, respectively. The interrogator, the receiver, and the tag are operative, in response to receipt of the respective parameter, to modify its operational characteristics in accordance with the respective parameter, thereby avoiding interference at the receivers and the tags.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 2, 2006
    Inventors: Pattabhiraman Krishna, Jeffrey Fischer, David Husak, Robert Stephenson
  • Publication number: 20060022801
    Abstract: An architecture of an RFID system that facilitates the accessing of RFID tag data within an RFID environment. The architecture includes a plurality of RFID readers, each reader being operative to transmit a first RF signal for scanning at least one RFID tag disposed within an RF coverage region associated with the reader, and to receive at least one second RF signal including tag data in response to the scanning of the tag. The architecture further includes at least one host computer operative to execute at least one client application, and at least one controller/processor communicably coupled to the plurality of readers and the at least one host computer. The controller/processor is operative to control operation of the plurality of readers, to process the tag data received by the plurality of readers, and to provide the processed tag data to the at least one host computer for use by the at least one client application executing thereon.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 2, 2006
    Inventors: David Husak, Robert Stephenson, Michael Grady, Scott Barvick, Pattabhiraman Krishna, Chilton Cabot, Jeffrey Fischer
  • Publication number: 20060019454
    Abstract: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.
    Type: Application
    Filed: May 25, 2005
    Publication date: January 26, 2006
    Applicant: RJ Mears, LLC
    Inventors: Robert Mears, Marek Hytha, Scott Kreps, Robert Stephenson, Jean Augustin Yiptong, Ilija Dukovski, Kalipatnam Rao, Samed Halilov, Xiangyang Huang
  • Publication number: 20060011905
    Abstract: A semiconductor device may include a semiconductor substrate and at least one active device adjacent the semiconductor substrate. The at least one active device may include an electrode layer, a high-K dielectric layer underlying the electrode layer and in contact therewith, and a superlattice underlying the high-K dielectric layer opposite the electrode layer and in contact with the high-K dielectric layer. The superlattice may include a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: May 25, 2005
    Publication date: January 19, 2006
    Applicant: RJ Mears, LLC
    Inventors: Robert Mears, Marek Hytha, Scott Kreps, Robert Stephenson, Jean Augustin Chan yiptong, Ilija Dukovski, Kalipatnam Rao, Samed Halilov, Xiangyang Huang
  • Publication number: 20050272239
    Abstract: A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 8, 2005
    Applicant: RJ Mears, LLC
    Inventors: Marek Hytha, Robert Stephenson, Scott Kreps
  • Publication number: 20050167649
    Abstract: A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The semiconductor device may further include a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. The superlattice may also include at least one second region therein including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.
    Type: Application
    Filed: April 1, 2005
    Publication date: August 4, 2005
    Applicant: RJ Mears, LLC
    Inventors: Robert Mears, Robert Stephenson
  • Publication number: 20050167653
    Abstract: A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may further include at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.
    Type: Application
    Filed: April 1, 2005
    Publication date: August 4, 2005
    Applicant: RJ Mears, LLC
    Inventors: Robert Mears, Robert Stephenson
  • Publication number: 20050170591
    Abstract: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. At least one second region may be formed in the superlattice including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.
    Type: Application
    Filed: April 1, 2005
    Publication date: August 4, 2005
    Applicant: RJ Mears, LLC
    Inventors: Robert Mears, Robert Stephenson