Patents by Inventor Robert Strenz

Robert Strenz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190057031
    Abstract: A method for updating a memory, which comprises several blocks, wherein each of the several blocks comprises multi-level cells and is operable in an MLC-mode or in a SLC-mode, wherein each multi-level cell may store more than one bit, wherein the method includes for each block to be updated: (a) copying the content of the block to a buffer block; (b) erasing the block; (c) writing the content of the block from the buffer block and an updated content for this block to this block, utilizing the capability of the block to be operated in the MLC-mode; (d) copying the updated content of the block to the buffer block; (e) erasing the block; and (f) writing the updated content from the buffer block to the block, utilizing the capability of the block to be operated in the SLC-mode. Also, therefore is a corresponding device.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 21, 2019
    Inventors: Thomas Kern, Robert Allinger, Robert Strenz
  • Patent number: 9887006
    Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line, wherein the first and second resistive elements are coupled between different metal layers; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: February 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Robert Strenz, Robert Allinger
  • Patent number: 9564403
    Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Robert Allinger, Karl Hofmann, Klaus Knobloch, Robert Strenz
  • Patent number: 9559108
    Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 31, 2017
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
  • Patent number: 9543398
    Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: January 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Matteo Dainese, Franz Hirler, Christian Jaeger, Maximilian Roesch, Wolfgang Roesner, Martin Stiftinger, Robert Strenz
  • Patent number: 9502468
    Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 22, 2016
    Assignee: Infineon Technologies AG
    Inventors: Robert Strenz, Robert Allinger
  • Publication number: 20160211250
    Abstract: According to various embodiments, a semiconductor substrate arrangement may be provided, wherein the semiconductor substrate arrangement may include: a semiconductor substrate defining a first area at a first level and a second area next to the first area at a second level, wherein the first level is lower than the second level; a plurality of planar non-volatile memory structures disposed over the semiconductor substrate in the first area; and a plurality of planar transistor structures disposed over the semiconductor substrate in the second area.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 21, 2016
    Inventors: Wolfram LANGHEINRICH, Robert STRENZ, Georg TEMPEL, Knut STAHRENBERG, Nikolaos HATZOPOULOS, Christoph BUKETHAL, Klaus KNOBLOCH, Achim GRATZ, Mayk ROEHRICH
  • Patent number: 9362498
    Abstract: A method of forming a memory includes forming a first electrode and a second electrode within a first layer over a semiconductor substrate, forming a resistive-switching memory element and an antifuse element over the first layer, wherein the resistive-switching memory element includes a metal oxide layer and is electrically contacting the first electrode, wherein the metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness, wherein the antifuse element includes a dielectric layer and is electrically contacting the second electrode, and wherein the dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage, and forming a third electrode and a fourth electrode within a second layer over the resistive-switching memory element and the antifuse element, wherein the third electrode is electrically contacting the resistive-switching memory element and the fourth electrode is elect
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 7, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Knobloch, Robert Strenz
  • Publication number: 20160056251
    Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 25, 2016
    Inventors: Johannes Georg Laven, Anton Mauder, Matteo Dainese, Franz Hirler, Christian Jaeger, Maximillian Roesch, Wolfgang Roesner, Martin Stiftinger, Robert Strenz
  • Publication number: 20150372230
    Abstract: A method of forming a memory includes forming a first electrode and a second electrode within a first layer over a semiconductor substrate, forming a resistive-switching memory element and an antifuse element over the first layer, wherein the resistive-switching memory element includes a metal oxide layer and is electrically contacting the first electrode, wherein the metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness, wherein the antifuse element includes a dielectric layer and is electrically contacting the second electrode, and wherein the dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage, and forming a third electrode and a fourth electrode within a second layer over the resistive-switching memory element and the antifuse element, wherein the third electrode is electrically contacting the resistive-switching memory element and the fourth electrode is elect
    Type: Application
    Filed: August 27, 2015
    Publication date: December 24, 2015
    Inventors: KLAUS KNOBLOCH, ROBERT STRENZ
  • Patent number: 9147840
    Abstract: A memory includes a first electrode and a second electrode formed within a first layer and includes a third electrode and a fourth electrode formed within a second layer. The memory includes a resistive-switching memory element and an antifuse element. The resistive-switching memory element includes a metal oxide layer and is disposed between the first electrode and the third electrode. The metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness. The antifuse element includes a dielectric layer and is disposed between the second electrode and the fourth electrode. The dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: September 29, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Knobloch, Robert Strenz
  • Publication number: 20150255509
    Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 10, 2015
    Applicant: Infineon Technologies AG
    Inventors: Robert STRENZ, Robert ALLINGER
  • Publication number: 20150255477
    Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 10, 2015
    Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
  • Publication number: 20150249211
    Abstract: A memory includes a first electrode and a second electrode formed within a first layer and includes a third electrode and a fourth electrode formed within a second layer. The memory includes a resistive-switching memory element and an antifuse element. The resistive-switching memory element includes a metal oxide layer and is disposed between the first electrode and the third electrode. The metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness. The antifuse element includes a dielectric layer and is disposed between the second electrode and the fourth electrode. The dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Applicant: Infineon Technologies AG
    Inventors: Klaus Knobloch, Robert Strenz
  • Patent number: 9040375
    Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: May 26, 2015
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
  • Patent number: 9030877
    Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Robert Strenz, Wolfram Langheinrich, Mayk Roehrich, Robert Wiesner
  • Publication number: 20150091109
    Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Infineon Technologies AG
    Inventors: Robert Allinger, Karl Hofmann, Klaus Knobloch, Robert Strenz
  • Publication number: 20140213049
    Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
  • Patent number: 8470670
    Abstract: One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: June 25, 2013
    Assignee: Infineon Technologies AG
    Inventors: John Power, Danny Pak-Chum Shum, Wolfgang Dickenscheid, Robert Strenz
  • Patent number: 8410815
    Abstract: A transistor arrangement includes a switch transistor and a sense transistor. The switch transistor includes a charge storing structure and a control structure. The sense transistor includes a charge storing structure, a control structure and a select structure. The charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor. The sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 2, 2013
    Assignee: Infineon Technologies AG
    Inventors: Robert Strenz, Klaus Knobloch