Abstract: A programmable resistive element is provided which includes a channel 16 comprising a layer of gallium arsenide. A programming barrier 18 is disposed outwardly from channel 16. A storage gate 20 comprising a layer of intrinsic gallium arsenide is disposed outwardly from programming barrier 18. An insulator 22, comprising a layer of aluminum-gallium-arsenide, is disposed outwardly from storage gate 20. A control gate 24 is disposed outwardly from insulator 22. First and second spaced apart contacts 26 and 28 contact channel 16.

Abstract: A read only memory whererin information is encoded in the pattern of coupling of column lines to changes of quantum-coupled wells linked by resonant tunneling, which constitute rows. it is not strictly necessary that each chain of quantum wells itself constitute one row, but the extremely close packing density of the quantum wells nevertheless permits a very high row density.

Abstract: A three-terminal quantum well device, which functions somewhat analogously to an MOS transistor. That is, the three terminals of the device can generally be considered as source, gate, and drain. An output contact is connected by tunneling to a number of parallel chains of quantum wells, each well being small enough that the energy levels in the well are quantized discretely. In each of these chains of wells, the second well is coupled to a common second conductor, and the first well is electronically coupled to a common first conductor.

Abstract: The present invention teaches a process for fabrication of quantum-well devices, in which the quantum-wells are configured as small islands of GaAs in an AlGaAs matrix. Typically these islands are roughly cubic, with dimensions of about 100 Angstroms per side. To fabricate these, an n- on n+ epitaxial GaAs structure is grown, and then is etched to an e-beam defined patterned twice, and AlGaAs is epitaxially regrown each time. This defines the quantum wells of GaAs in the AlGaAs matrix, and output contacts are then easily formed.

Abstract: The present invention teaches a process for fabrication of quantum-well devices, in which the quantum-wells are configured as small islands of GaAs in an AlGaAs matrix. Typically these islands are roughly cubic, with dimensions of about 100 Angstroms per side. To fabricate these, an n- on n+ epitaxial GaAs structure is grown, and then is etched to an e-beam defined patterned twice, and AlGaAs is epitaxially regrown each time. This defines the quantum wells of GaAs in an AlGaAs matrix, and output contacts are then easily formed.

Abstract: The invention is embodied in a non-volatile metal-insulator-semiconductor having a novel combination of insulating layers including a silicon nitride layer covered by a silicon dioxide layer covered by a high dielectric constant insulator. In one embodiment of the invention the nitride layer is directly upon the semiconductor. In another embodiment the insulator combination also includes a second layer of silicon dioxide located between the nitride layer and the semiconductor. Writing is accomplished by injection of charge into the nitride layer and shifting the threshold voltage of the structure. Erasure is accomplished by forcing the injected charge back into the semiconductor to recombine with majority carriers. The charge can be electrons or holes depending on the semiconductor type. The memory element of the invention has lower write/erase voltages, shorter write/erase times and higher writing efficiency.

Abstract: Non-volatile metal-insulator-semiconductor memory elements are fabricated using a novel sequence of steps for forming multiple dielectric layers including particularly a layer of titanium dioxide covering a layer of silicon dioxide covering a layer of silicon nitride. The titanium dioxide of a type known as rutile is formed by evaporation of titanium upon the silicon dioxide and oxidization of the titanium in an oxygen ambient at high temperatures.

Abstract: Non-volatile metal-insulator-semiconductor memory elements are fabricated using a novel sequence of steps for forming multiple dielectric layers including particularly a layer of titanium dioxide covering a layer of silicon dioxide covering a layer of silicon nitride. The titanium dioxide of a type known as rutile is formed by evaporation of titanium upon the silicon dioxide and oxidization of the titanium in an oxygen ambient at high temperatures.

Abstract: The invention is embodied in a non-volatile metal-insulator-semiconductor having a novel combination of insulating layers including a silicon nitride layer covered by a silicon dioxide layer covered by a high dielectric constant insulator. In one embodiment of the invention the nitride layer is directly upon the semiconductor. In another embodiment the insulator combination also includes a second layer of silicon dioxide located between the nitride layer and the semiconductor. Writing is accomplished by injection of charge into the nitride layer and shifting the threshold voltage of the structure. Erasure is accomplished by forcing the injected charge back into the semiconductor to recombine with majority carriers. The charge can be electrons or holes depending on the semiconductor type. The memory element of the invention has lower write/erase voltages, shorter write/erase times and higher writing efficiency.

Abstract: A semiconductor body has formed on it at least two hall effect plates each having a pair of oppositely positioned current contacts and a pair of oppositely positioned hall voltage contacts, the hall effect plates being positioned with respect to each other such that a line of one bisecting the current terminals is generally orthogonal to a line of the other bisecting the current terminals. Means are provided for applying a voltage across the current terminals of both of the hall plates and means are provided for selectively applying a magnetic field that intersects substantially perpendicularly the plane of the hall plates. The positive hall voltage contacts are connected together and the negative hall voltage contacts are connected together, with output circuitry connected to this interconnecting circuitry for receiving and transmitting an electrical signal indicative of the presence of the intersecting magnetic field.

Abstract: The specification discloses a read only memory constructed from a charge coupled device having a channel for storage of charges in bit regions defined along the channel. Various structures are disclosed for storing combinations of two different levels of charge in the bit regions. In one embodiment, storage gates which communicate at spaced points along the length of the CCD channel are provided with different widths to control the level of charge input by the storage gates to the channel bit regions. In alternate embodiments, the semiconductor doping or oxide thickness of the storage gates are controlled in order to cause different levels of charge to be stored in the channel gate bit regions. After storage of the different charge levels in the channel, phase electrodes which span the channel are operated to serially output the charge levels from the channel to provide a predetermined digital word.

Abstract: A charge coupled device for infrared imaging covered with a layer of insulation for absorbing infrared patterns and generating signals due to the temperature dependence of dark current in the charge coupled device.