Patents by Inventor Robert T. Carroll

Robert T. Carroll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11601052
    Abstract: An apparatus comprises an emulator and a corresponding compensator. During operation, the emulator produces, at different instants of time, an emulated output current value representative of an amount of current supplied from an output voltage to a load. In general, the compensator provides selective compensation to the emulated output current value over time. For example, for a first time duration, compensation adjustments from the compensator are used to modify the emulated output current value. For a second duration of time, compensation adjustments from the compensator are not used to modify the emulated output current value. Disabling or discontinuing application of adjustments (such as based on the actual measured output current) during the second time duration (such as during a respective transient condition) provides more accurate and timely generation of a respective emulated output current value.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: March 7, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Venkat Sreenivas, Robert T. Carroll, Charles P. Amirault, James R. Garrett
  • Publication number: 20210336543
    Abstract: An apparatus comprises an emulator and a corresponding compensator. During operation, the emulator produces, at different instants of time, an emulated output current value representative of an amount of current supplied from an output voltage to a load. In general, the compensator provides selective compensation to the emulated output current value over time. For example, for a first time duration, compensation adjustments from the compensator are used to modify the emulated output current value. For a second duration of time, compensation adjustments from the compensator are not used to modify the emulated output current value. Disabling or discontinuing application of adjustments (such as based on the actual measured output current) during the second time duration (such as during a respective transient condition) provides more accurate and timely generation of a respective emulated output current value.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Inventors: Venkat Sreenivas, Robert T. Carroll, Charles P. Amirault, James R. Garrett
  • Patent number: 10707160
    Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 7, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Robert T. Carroll
  • Patent number: 10483193
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Publication number: 20190148272
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Application
    Filed: January 15, 2019
    Publication date: May 16, 2019
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 10224266
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 10044270
    Abstract: A control circuitry can be configured to receive an error signal indicating a difference between an output voltage of the power supply and a desired setpoint for the output voltage. According to one configuration, depending on the error signal, the control circuitry initiates switching between operating the control circuitry in a pulse width modulation mode and operating the control circuitry in a pulse frequency modulation mode to produce an output voltage. Operation of the control circuitry in the pulse frequency modulation mode during a transient condition, such as when a dynamic load instantaneously requires a different amount of current, enables the power supply to satisfy current consumption by the dynamic load. Subsequent to the transient condition, the control circuitry switches back to operation in the pulse width modulation mode.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 7, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Venkat Sreenivas, Robert T. Carroll
  • Publication number: 20180076124
    Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventor: Robert T. Carroll
  • Patent number: 9831168
    Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Robert T. Carroll
  • Publication number: 20170063235
    Abstract: A control circuitry can be configured to receive an error signal indicating a difference between an output voltage of the power supply and a desired setpoint for the output voltage. According to one configuration, depending on the error signal, the control circuitry initiates switching between operating the control circuitry in a pulse width modulation mode and operating the control circuitry in a pulse frequency modulation mode to produce an output voltage. Operation of the control circuitry in the pulse frequency modulation mode during a transient condition, such as when a dynamic load instantaneously requires a different amount of current, enables the power supply to satisfy current consumption by the dynamic load. Subsequent to the transient condition, the control circuitry switches back to operation in the pulse width modulation mode.
    Type: Application
    Filed: November 10, 2016
    Publication date: March 2, 2017
    Inventors: Venkat Sreenivas, Robert T. Carroll
  • Patent number: 9577522
    Abstract: A hybrid power supply circuit includes a digital circuit, a digital-to-analog converter circuit, and an analog compensator circuit (analog control circuit). According to one configuration, the digital circuit includes a digital pre-filter that substantially matches settings of analog filter circuitry present in the analog compensator circuit. During operation, the digital circuit receives control input indicating how to control a magnitude of an output voltage produced by the power supply circuit. The digital circuit passes the received through the digital pre-filter to produce a (filtered) digital reference voltage. The digital-to-analog converter circuit converts the received digital reference voltage into an analog reference voltage (a filtered rendition of the received control input). The analog compensator circuit receives and uses the digitally pre-filtered analog reference voltage as a basis to control the magnitude of the output voltage produced by the power supply circuit.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Saurabh Jayawant, Venkat Sreenivas, Parviz Parto, Robert T. Carroll
  • Patent number: 9531266
    Abstract: A control circuitry can be configured to receive an error signal indicating a difference between an output voltage of the power supply and a desired setpoint for the output voltage. According to one configuration, depending on the error signal, the control circuitry initiates switching between operating the control circuitry in a pulse width modulation mode and operating the control circuitry in a pulse frequency modulation mode to produce an output voltage. Operation of the control circuitry in the pulse frequency modulation mode during a transient condition, such as when a dynamic load instantaneously requires a different amount of current, enables the power supply to satisfy current consumption by the dynamic load. Subsequent to the transient condition, the control circuitry switches back to operation in the pulse width modulation mode.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Venkat Sreenivas, Robert T. Carroll
  • Publication number: 20160307828
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Publication number: 20160261182
    Abstract: A hybrid power supply circuit includes a digital circuit, a digital-to-analog converter circuit, and an analog compensator circuit (analog control circuit). According to one configuration, the digital circuit includes a digital pre-filter that substantially matches settings of analog filter circuitry present in the analog compensator circuit. During operation, the digital circuit receives control input indicating how to control a magnitude of an output voltage produced by the power supply circuit. The digital circuit passes the received through the digital pre-filter to produce a (filtered) digital reference voltage. The digital-to-analog converter circuit converts the received digital reference voltage into an analog reference voltage (a filtered rendition of the received control input). The analog compensator circuit receives and uses the digitally pre-filtered analog reference voltage as a basis to control the magnitude of the output voltage produced by the power supply circuit.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 8, 2016
    Inventors: Saurabh Jayawant, Venkat Sreenivas, Parviz Parto, Robert T. Carroll
  • Patent number: 9390944
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: July 12, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 9171743
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Publication number: 20150255384
    Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 10, 2015
    Inventor: Robert T. Carroll
  • Patent number: 9070670
    Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: June 30, 2015
    Assignee: International Rectifier Corporation
    Inventor: Robert T. Carroll
  • Patent number: 8907643
    Abstract: A power supply system includes a PID control circuit, a signal shaping circuit, and a PWM control circuit. The PID control circuit generates a signal based on an error voltage of the power supply system. The signal shaping circuit receives and converts the signal outputted from the PID control circuit into a linear control signal. To reduce cost, the shaping circuit can include a piecewise linear implementation. During non-transient load conditions, the PWM control circuit utilizes the linear control signal outputted from the signal shaping circuit to adjust a switching period of a power supply control signal. The switching period of the power supply control signal is maintained within a desired range. During transients, settings of the PID control circuit are modified to provide a faster response. The switching period of the power supply control signal may be adjusted outside of the desired frequency range.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: December 9, 2014
    Assignee: International Rectifier Corporation
    Inventors: Venkat Sreenivas, Robert T. Carroll
  • Publication number: 20140312858
    Abstract: A control circuitry can be configured to receive an error signal indicating a difference between an output voltage of the power supply and a desired setpoint for the output voltage. According to one configuration, depending on the error signal, the control circuitry initiates switching between operating the control circuitry in a pulse width modulation mode and operating the control circuitry in a pulse frequency modulation mode to produce an output voltage. Operation of the control circuitry in the pulse frequency modulation mode during a transient condition, such as when a dynamic load instantaneously requires a different amount of current, enables the power supply to satisfy current consumption by the dynamic load. Subsequent to the transient condition, the control circuitry switches back to operation in the pulse width modulation mode.
    Type: Application
    Filed: June 30, 2014
    Publication date: October 23, 2014
    Inventors: Venkat Sreenivas, Robert T. Carroll