Abstract: To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.

Abstract: A manufacturing process for producing dynamic random access memories (DRAMs) having redundant components includes steps for concurrently forming normal (i.e. non-fused) contacts to components of the DRAMs and anti-fused contacts to the redundant components. The process by which the normal and anti-fused contacts are made is readily implemented using standard integrated circuit processing techniques. An anti-fuse contact (20) and a normal (i.e. non-fused) contact (10) are formed by opening respective contact areas in a dielectric (110), selectively forming an insulating layer (210) over the anti-fuse contact, applying polysilicon (212, 410) to cover the insulating layer of the anti-fuse contact and to fill the opening over the normal contact. In one embodiment of the invention, the circuit region served by the anti-fuse contact is subject to ion implantation (810) to improve its conductivity before the anti-fuse contact is formed.

Abstract: A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Abstract: An integrated circuit includes a plurality of CMOS transistors formed in a monocrystalline substrate. Within the substrate is a plurality of complementary spaced pairs of a p-well region and a n-well region. Between each well region, each of which has a source, gate, and drain, is a self-aligned trench filled with semiconductor material. A method of fabricating a field effect transistor entails a first step of forming a layer of first insulative material over a monocrystalline substrate. Next, a layer of semiconductor material is formed over the first insulative material. A p- or n-well masking layer is formed over the semiconductor layer and patterned to expose a first portion of the underlying semiconductor layer. A first dopant of one polarity is implanted in the region of the substrate aligned with the semiconductor layer first portion, which is then converted into a second insulative material. The masking layer is removed, thereby exposing the remaining portion of the semiconductor layer.

Abstract: The present invention is directed to a silicon carbide field effect transistor. The FET is formed on a silicon carbide monocrystalline substrate. An insulative material gate having a pair of spaced apart sidewalls is patterned on the substrate. The insulative material comprises a first insulation material overlayed by an electrically conductive layer. Within the substrate is lightly doped base regions located partially under the sidewalls of the gate and extending into the exposed substrate. Associated with the lightly doped base regions are heavily doped source regions aligned with the exposed substrate. On the underside of the substrate is a drain region to form the FET. Further in accordance with the present invention, a method to fabricate a field effect transistor is disclosed. The transistor is formed in a monocrystalline substrate of silicon carbide. Forming a transistor on the silicon carbide substrate entails depositing a first electrically insulative layer over the substrate.

Abstract: A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Abstract: The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a gate that is provided on both sides with an insulating spacer to electrically isolate it from the source and drain. The planarized tungsten layer comprises a first portion whose lower surface is in contact with a polysilicon layer of the gate. The lower surface of each of the second and third portions of the tungsten layer is in contact with the source and drain, respectively. The second and third portions are insulated from the first portion by the insulating spacers, and the upper surfaces of all the portions comprise a coplanar surface. Planarization of the deposited metal layer thus provides ohmic contact at substantially the same level to the source, drain, and gate.

Abstract: A radiation hardening isolation technique uses a poly buffered LOCOS structure (34, 36) to protect the device areas during field oxide 40 formation. The field oxide 40 is removed, and the polysilicon structure 34 is covered with a PSG or BPSG layer 42. Layer 42 is planarized and the polysilicon 34 is removed to provide a self-aligned device region 31.

Abstract: A semiconductor material is overlayed with sequentially stacked layers including a protective layer, an affinity layer having an affinity for a second implant blocking material comprising tungsten, a first implant blocking layer and a masking layer having a first pattern. A portion of the first blocking layer not being masked is removed to expose a first portion of the affinity layer and a first dopant is implanted into the underlying semiconductor through the exposed first portion of the affinity layer. The mask is removed to expose the first blocking layer and a second blocking layer is formed from the second blocking material over the exposed first portion of the affinity layer but not over the exposed first blocking layer. The first blocking layer is removed to expose a second portion of the affinity layer which constitutes a second pattern. A second dopant is implanted into the underlying semiconductor through the exposed second portion of the affinity layer.

Abstract: A modular rack for holding and displaying carpet samples. The rack has sloping spaced-apart baffles that form slots to receive the samples. The underside of the rack has attachment means to attach to a grip on a stand. Preferably the grid includes parallel rods to which hook-like attachment means are engaged.

Abstract: A method of fabricating a semiconductor device having a symmetric and complementary P-well and N-well. The novel method involves the introduction of a first dopant type into a semiconductor substrate directly through those regions of an oxide layer and a nitride layer which do not underlie a first mask layer. The first mask layer is removed and a second mask layer is formed. A complementary dopant type is then introduced into the semiconductor substrate directly through those regions of the oxide layer and nitride layer which do not underlie the second mask layer. The second mask layer is removed and the dopant ions are simultaneously subjected to thermal drive in to thereby form adjacent wells of opposite dopant type in the semiconductor substrate.

Abstract: A stand to hold and display pieces of flat material such as carpet samples. The stand includes an upright spindle and a sample support structure. The sample support structure includes a support ring and a spreader or series of spreaders below the ring. The spreader projects radially outward beyond the support ring. Attachment devices releasably join the samples to the support ring and have a substantial dimension of length which allows the samples to hang so as freely to rest against each other and against the spreader in a shingled and spread-out relationship.

Abstract: A holder for stiffly flexible sheets such as flooring samples which are likely to curl at their edges and corners. The holder has a proximal edge, a distal edge, and two side edges connecting the proximal and distal edges. The edges form a top central opening through which a sheet in the holder can be seen. Each of the four edges has a top rail to restrain the sheet from upward movement. The proximal edge has a bottom restraint and an edge restraint to restrain the sheet at that edge. A bottom support extends across the area bounded by the edges to give underlying support to the sheet. The top rail at the distal edge is shaped concavely to form a deflector to deflect the leading edge of a sheet inserted into the holder. Mounting pins can be provided for mounting the holder to a stand. The deflector deflects the leading edge of the sheet which it confronts into a channel. Mounting pins can be provided for mounting the holder to the stand.

Abstract: A display rack device wherein flat articles such as carpet samples can be displayed in a shingled manner so as to show a portion of a plurality of displays and the major portion of at least the top one of said displays.

Abstract: A display system for displaying samples, for example, floor covering samples such as carpets and rugs. A perforated support board supports samples which are removably attached thereto by separable fasteners. Stand means may be provided to hold the support board. Samples may be shingled or displayed side-by-side, and the apertures in the support board are arranged so as to permit a variety of display patterns.