Abstract: A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy.

Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.

Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.

Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.

Abstract: A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.

Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.

Abstract: According to some embodiments, an arrangement is provided for cooling a heat-generating device, including a memory module (e.g., a small outline dual inline memory module), in a system such as a laptop computer. The arrangement includes a heat spreader having a first section including at least one thermally conductive coupling member to thermally engage surfaces of electronic components on the heat-generating device and a second section including at least one spring member to cause pressurized engagement between the first section and the surfaces of the electronic components. The heat spreader may further be thermally coupled to a heat exchanger or a keyboard from which the heat is dissipated. Other embodiments are also described and claimed.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: A power control circuit and corresponding technique for controlling the reduction or augmentation of operating frequency and/or supply voltage utilized by an electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is interconnected to an external source having at least one enhanced cooling mechanism. As a result, the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage during other situations.

Abstract: A power control circuit and corresponding technique for controlling the reduction or augmentation of operating frequency and/or supply voltage utilized by an electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is interconnected to an external source having at least one enhanced cooling mechanism. As a result, the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage during other situations.

Abstract: A system for regulating power in a mobile electronics device uses "hint" NOP instructions having a reserved field of bits that generate control signals to affect an increase or decrease in power dissipation. The control signals raise or lower the operating potential provided by a power supply and also adjust the frequency of a clock signal in accordance with the information provided by the NOP instruction. Power is reduced for code sequences that could be executed more slowly, or the device is otherwise idle, without affecting the user's perception of overall system performance.

Abstract: A power control circuit and corresponding technique for reducing power consumption by an electronic device and thereby increasing performance. The power control circuit comprises a controller, a clock generation circuit and a power supply circuit. The controller detects whether a condition exists to scale the voltage and frequency of the electronic device and in response, signals the clock generation circuit to perform frequency scaling on the electronic device and the power supply circuit to perform voltage scaling on the electronic device. The condition may include a situation where the temperature of the electronic device is detected to have exceeded a thermal band. The condition may also include a situation where the electronic device is detected to be idle for a selected percentage of its run time.

Abstract: A device and method for power management of direct memory access ("DMA") slaves through DMA traps. The device comprises a plurality of registers coupled with conventional logic in order to generate a control signal for disabling direct memory access transfer requests for a powered-off DMA slave until the slave is re-powered. The method for managing power comprises steps of unmasking bits in a register containing information regarding which DMA slaves have been powered-off. Next, the DMA Controller consults a power management macro ("PMM") to determine whether a DMA transfer request involves a powered-off DMA slave. If not, the DMA transfer continues. However, if the DMA transfer does involve a powered-off DMA slave, then a main software application in operation is temporarily halted and the PMM generates a SMI signal and outputs the SMI signal to the central processing unit ("CPU") while keeping the disable control signal asserted, which effectively disables the DMA channel.

Abstract: The present invention relates to an apparatus and method for controlling a CPU clock in response to certain events with a system in order to conserve power usage. These events can be programmably enabled or disabled. The apparatus comprises a circuit for detecting enabled Stop Clock events requiring the CPU clock to temporarily cease operation. In combination therewith, the present invention includes a circuit for detecting enabled Stop Break events which are used to re-start the CPU clock. The present invention further comprises a Speedup circuitry to increase the CPU clock speed for enabled speedup events which are dependent on CPU clock speed.

Abstract: An information processing system, comprising a central processing unit (CPU); a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; a second system bus connected to the CPU; a host bridge connecting the second system bus to a peripheral bus having at least one peripheral device attached thereto, the host bridge including register space for storing information related to transactions occurring over the peripheral bus; and error capture logic incorporated into the host bridge. The error capture logic monitors the transactions occurring over the peripheral bus, detects parity errors occurring during any of the transactions, and generates an interrupt routine over the second system bus to the CPU. The CPU reads the register space and performs necessary recovery operations.

Abstract: Chip logic, a frequency multiplication and/or division, a temperature sensing circuit, and a power management circuit, are integrated on a very large scale integrated (VLSI) circuit chip. The temperature sensing circuit directly measures the chip temperature, producing a temperature output signal. The power management circuit, which is connected to the temperature sensing circuit and to the chip logic, responds to the temperature output signal and to a functional state of the chip logic to generate a control signal to the PLL. The PLL responds to the control signal to either stop the clock signal or modify the operating frequency of the clock signal, depending upon the state of the control signal.

Abstract: An adapter ring construction and cooperative arrangement with respect to an arbor for installing tooling on arbors or shafts such as the rotary disc shear knives which are mounted on arbors of slitters for strip metal slitting lines which are operated to continuously slit multiple strands from a wider continuously moving strip such as strip steel. The adapter comprises a ring-like member which is threaded onto a reduced threaded arbor stub shaft of each slitter arbor, after removal of clamping nuts from the stub shafts and retraction of the outboard bearing housing for a pair of cooperating parallel rotary shear knife mounting arbors. The ring-like adapter has a special outer annular contour in cross section which facilitates easy, rapid and damage-free telescoping of rotary shear knives and spacers onto the arbor for a changeover of desired spacing of the rotary knives when the desired strand widths of multiple strands to be slit are changed.