Abstract: A data processing system, having a volatile main memory prepares for power supply failure, at the first instance of power supply potential falling below a predetermined limit, by readying its current task for restart, data-saving by storing the contents of volatile, processor registers in the main memory, and completing any non-postponable tasks. If power deficiency lasts for longer than a predetermined period, the memory is maintained by a battery power source if and only if data-saving has been completed. Restoration of power during the predetermined period causes instant reversal and restart, but after the elapse of the predetermined period, causes reversal and restart if and only if a data save has been completed, otherwise causing reinitialization.

Abstract: An apparatus and method of utilizing a group of partially defective memory devices in conjunction with a single faultfree memory device to form an effectively faultfree memory unit. Each of the partial devices and the faultfree device are characterized as requiring an address input to be presented in two segments at separate times during an access cycle. Each of the partial devices is characterized as having all of its respective faults within a contiguous address space, the group of partial devices configured to form one continuous addressable storage area. The first segment of the input address is presented to the group of partial devices and the faultfree device, and then a first stage access is initiated to all devices. Concurrently, the second segment of the input address is compared with the address combination which defines the faulty areas of the partial devices being accessed.