Patents by Inventor Robert T. Narumi

Robert T. Narumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Complex layout-based topological data analysis of analog netlists to extract hierarchy and functionality
    Patent number: 9367659
    Abstract: A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: June 14, 2016
    Assignee: Raytheon Company
    Inventors: Parviz Saghizadeh, Thomas Allen Spargo, Robert T. Narumi, Mark W. Redekopp
  • COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY
    Publication number: 20150100928
    Abstract: A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.
    Type: Application
    Filed: August 7, 2014
    Publication date: April 9, 2015
    Inventors: Parviz Saghizadeh, Thomas Allen Spargo, Robert T. Narumi, Mark W. Redekopp
  • Method of detecting changes in integrated circuits using thermally imaged test patterns
    Patent number: 8818741
    Abstract: A method of testing an electrical circuit includes applying test vectors to a circuit, detecting thermal changes in portions of the circuit during application of the test vectors, and identifying unexpected activity corresponding to the thermal changes. The method supplements standard testing techniques to provide a new method of assessing operation of fabricated integrated circuits and programmed field programmable gate arrays.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: August 26, 2014
    Assignee: Raytheon Company
    Inventors: Robert T. Narumi, Parviz Saghizadeh
  • METHOD OF DETECTING CHANGES IN INTEGRATED CIRCUITS USING THERMALLY IMAGED TEST PATTERNS
    Publication number: 20100256933
    Abstract: A method of testing an electrical circuit includes applying test vectors to a circuit, detecting thermal changes in portions of the circuit during application of the test vectors, and identifying unexpected activity corresponding to the thermal changes. The method supplements standard testing techniques to provide a new method of assessing operation of fabricated integrated circuits and programmed field programmable gate arrays.
    Type: Application
    Filed: April 3, 2009
    Publication date: October 7, 2010
    Inventors: Robert T. NARUMI, Parviz Saghizadeh
  • Self-calibrating, self-correcting transceivers and methods
    Patent number: 6118811
    Abstract: A transceiver has a digital signal processor which can insert calibration signals of known level and frequency into transmitters for calibration and correction of transmitter parameters. An output of the calibrated and corrected transmitter is subsequently coupled into a calibration mixer along with a mixing signal (e.g., from a local oscillator generator. The outputs of the calibration mixer have known levels and frequencies and are inserted into receivers for calibration and correction of receiver parameters.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: September 12, 2000
    Assignee: Raytheon Company
    Inventors: Robert T. Narumi, Lloyd F. Linder, Erick M. Hirata, Don C. Devendorf, Matthew S. Gorder, Phung N. Phan, Ricky Y. Chen