Abstract: A system for implementing a repeater interlock scheme between a first and a second bus utilizes two repeaters. The first repeater coupled to the first bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second repeater which is coupled to memory through the second bus. The transaction buffer passes the interlock data for memory to the second bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands. The interlock buffer waits for an unlock write signal before retrying an interlock transaction thus alleviating congestion on the second bus.

Abstract: A system for implementing a bus window interlock scheme between a first and a second bus utilizes two bus window modules. The first bus window module coupled to the processor bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second bus window module which is coupled to memory through the memory bus. The transaction buffer passes the interlock data for memory to the memory bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands.

Abstract: A clock apparatus provides variable frequency system clock signals for synchronizing the operation of data processing apparatus and constant frequency timing signals, in phase with the system clock signals, for controlling the operation of an interval timer or related apparatus. The variable frequency system clock signals are produced by placing a controllable divider network in the phase locked loop. The input signals to the controllable divider network are distributed as the system clock signals. The constant frequency is obtained by distributing count signals from the controllable divider network of the phase locked loop circuit to a plurality of comparator circuits and output signals from the comparator provide a multiplicity of timing intervals that result in the constant frequency signals. The timing intervals are determined by the control signals that are applied to controllable divider network and to a plurality of divider circuits associated with the comparator circuits.