Patents by Inventor Robert T. Trabucco
Robert T. Trabucco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6088914Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.Type: GrantFiled: October 30, 1997Date of Patent: July 18, 2000Assignee: LSI Logic CorporationInventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
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Patent number: 5989937Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.Type: GrantFiled: August 26, 1997Date of Patent: November 23, 1999Assignee: LSI Logic CorporationInventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
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Patent number: 5901437Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.Type: GrantFiled: October 30, 1997Date of Patent: May 11, 1999Assignee: LSI Logic CorporationInventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
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Patent number: 5899737Abstract: A fluxless method for fusing preformed solder balls to contact pads on a semiconductor package substrate wherein a masking plate having one or more vertical holes corresponding to the contact pads is placed over the package substrate, oxide-free solder balls are placed in the holes, the assembly is preheated to a temperature less than the melting point of the solder, and an energetic beam is directed onto the preformed solder balls to melt them and fuse them to the contact pads.Type: GrantFiled: September 20, 1996Date of Patent: May 4, 1999Assignee: LSI Logic CorporationInventor: Robert T. Trabucco
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Patent number: 5761048Abstract: According to the present invention, a method is provided for attaching a package substrate to a circuit board. In one version of the invention, the package substrate has a semiconductor die disposed thereon, and the semiconductor die has a plurality of bond pads formed thereon which are electrically connected to conductive traces on the package substrate. In one embodiment of the invention, the method comprises the steps of attaching a first surface of an electrical connector to one of the conductive traces by thermoplastic adhesion; and attaching a second surface of the electrical connector to a conducting pad on the circuit board, also by thermoplastic adhesion.Type: GrantFiled: April 16, 1996Date of Patent: June 2, 1998Assignee: LSI Logic Corp.Inventor: Robert T. Trabucco
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Patent number: 5745986Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit on a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.Type: GrantFiled: July 24, 1995Date of Patent: May 5, 1998Assignee: LSI Logic CorporationInventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
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Patent number: 5610442Abstract: A planar substrate is attached to a face of a semiconductor die. The semiconductor die is electrically connected to a printed wiring board and encapsulation material covers the peripheral edges of the planar substrate, semiconductor die, and means for interconnecting the die and printed wiring board. An exterior face of the planar substrate remains exposed and may be utilized in pick and place automatic assembly. The exterior face of the planar substrate may also be utilized for attachment of an external heat sink for improved heat transfer from the semiconductor device. The planar substrate may be comprised of silicon, ceramic, metal or any other stiff material so long as the temperature coefficient of expansion is similar to that of the semiconductor die. A flip-chip semiconductor die may also be utilized without a planar substrate wherein the nonactive face of the die is exposed.Type: GrantFiled: March 27, 1995Date of Patent: March 11, 1997Assignee: LSI Logic CorporationInventors: Mark R. Schneider, Robert T. Trabucco
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Patent number: 5435482Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.Type: GrantFiled: February 4, 1994Date of Patent: July 25, 1995Assignee: LSI Logic CorporationInventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
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Patent number: 5388327Abstract: A technique for simultaneously forming large numbers of solder ball (or bump) contacts on a surface of a substrate is described. A dissolvable film carrier is provided with holes arranged in a shape to correspond to an array of contact pads on a substrate. The holes are filled with solder. The film carrier retains the solder. The carrier is placed over the surface of the substrate and is heated, causing the solder to re-flow and to wet and to adhere to the contact pads. The carrier, which resists the re-flow temperature, maintains the shape of the solder contacts while cooling. After cooling, the film carrier can be removed from around the solder contacts with a suitable solvent.Type: GrantFiled: September 15, 1993Date of Patent: February 14, 1995Assignee: LSI Logic CorporationInventor: Robert T. Trabucco
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Patent number: 5381848Abstract: A technique for simultaneously forming large numbers of solder ball (or bump) contacts on a surface of a substrate is described. A mold is provided for receiving a substrate. Recesses in the mold are shaped to form contacts of a desired size, and are arranged to align with contact pads on the surface of the substrate. When the substrate is inserted into the mold and the mold is closed, the contact pads align with the recesses. Molten solder is introduced into the recesses and, upon cooling, forms conductive raised bump contacts on the contact pads. The substrate is then removed from the mold. Various features of the invention are directed to forming "tall" contacts with an aspect ratio (height to width ratio) of greater than 1:1, processing more than one substrate at a time, processing substrates of different sizes, and processing substrates with different contact patterns.Type: GrantFiled: September 15, 1993Date of Patent: January 17, 1995Assignee: LSI Logic CorporationInventor: Robert T. Trabucco