Abstract: Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly interesting application in polyimide filled deep trench isolated integrated circuits.The trench sidewalls are coated with an insulating material which is removed from the trench bottom at the all contact etch step. The Pt-Si is formed at the bottom of the trenches at the same time that the device contacts are made.

Abstract: The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps:(a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill,(b) blanket depositing the stud forming metal onto the whole structure,(c) lifting off said mask and the overlying metal,(d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height,(e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and(f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.

Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls by precluding significant variation in etch bias during the trench formation.

Abstract: A method of preventing out-gassing from lift-off structures formed of positive resists (as for example, o-quinone diazide/phenol formaldehyde novolak resins) during vacuum evaporation of metals in the fabrication of semiconductor devices. Such outgassing is avoided by compositional control of the photosensitive resist lift-off layer and by providing an additional baking step after the lift-off mask has been formed. Both conditions are required and critical to avoid the volatile resin decomposition products which not only tend to contaminate the device substrate surface, but also the deposited metal film. The method employs a photosensitive polymer which contains about 10 to 20 wt. % of the sensitizer (e.g. o-quinone diazide) in conjunction with a secondary baking step at about 160.degree. to about 200.degree. C. after the lift-off mask has been formed and prior to metal film deposition.