Patents by Inventor Robert Thomas Long
Robert Thomas Long has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7656170Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.Type: GrantFiled: February 14, 2007Date of Patent: February 2, 2010Assignee: KLA-Tencor Technologies CorporationInventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V. S. Satya, Padma A. Satya, legal representative, Robert Thomas Long, David J. Walker
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Publication number: 20080246030Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: ApplicationFiled: February 14, 2007Publication date: October 9, 2008Inventors: Akella V.S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas, Padma A. Satya
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Publication number: 20080237487Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.Type: ApplicationFiled: February 14, 2007Publication date: October 2, 2008Inventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V.S. Satya, Robert Thomas Long, David J. Walker, Padma A. Satya
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Patent number: 7012439Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.Type: GrantFiled: February 15, 2005Date of Patent: March 14, 2006Assignee: KLA-Tencor Technologies CorporationInventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V. S. Satya, Robert Thomas Long, David J. Walker
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Patent number: 6921672Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: GrantFiled: January 7, 2003Date of Patent: July 26, 2005Assignee: KLA-Tencor Technologies CorporationInventors: Akella V. S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas
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Patent number: 6867606Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.Type: GrantFiled: March 13, 2003Date of Patent: March 15, 2005Assignee: KLA-Tencor Technologies, Inc.Inventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V. S. Satya, Robert Thomas Long, David J. Walker
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Patent number: 6813572Abstract: Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.Type: GrantFiled: October 24, 2002Date of Patent: November 2, 2004Assignee: KLA-Tencor Technologies CorporationInventors: Akella V.S. Satya, Li Song, Robert Thomas Long, Kurt H. Weiner
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Patent number: 6751519Abstract: Disclosed are methods and apparatus for efficiently managing IC chip yield learning. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information includes a systematic yield (Y0), a defect density (DD), and a defect clustering factor (&agr;) determined based on the inspected test structure's yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer-sort test yield may be predicted at any stage in the fabrication process based on the running-average yield information maintained for previously fabricated wafer lots.Type: GrantFiled: October 24, 2002Date of Patent: June 15, 2004Assignee: KLA-Tencor Technologies CorporationInventors: Akella V. S. Satya, Li Song, Robert Thomas Long, Kurt H. Weiner
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Publication number: 20030155927Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.Type: ApplicationFiled: March 13, 2003Publication date: August 21, 2003Applicant: KLA Tencor Technologies CorporationInventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V.S. Satya, Robert Thomas Long, David J. Walker
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Patent number: 6576923Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.Type: GrantFiled: June 21, 2002Date of Patent: June 10, 2003Assignee: KLA-Tencor CorporationInventors: Akella V. S. Satya, Robert Thomas Long, Lynda C. Mantalas, Gustavo A. Pinto, Neil Richardson
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Publication number: 20030097228Abstract: Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.Type: ApplicationFiled: October 24, 2002Publication date: May 22, 2003Applicant: KLA-Tencor Technologies, CorporationInventors: Akella V.S. Satya, Li Song, Robert Thomas Long, Kurt H. Weiner
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Publication number: 20030096436Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: ApplicationFiled: January 7, 2003Publication date: May 22, 2003Applicant: KLA-Tencor Technologies CorporationInventors: Akella V. S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas
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Patent number: 6566885Abstract: A sample is inspected. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.Type: GrantFiled: August 25, 2000Date of Patent: May 20, 2003Assignee: KLA-TencorInventors: Gustavo A. Pinto, Brian C. Leslie, David L. Adler, Akella V. S. Satya, Robert Thomas Long, David J. Walker
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Patent number: 6528818Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: GrantFiled: August 25, 2000Date of Patent: March 4, 2003Assignee: KLA-TencorInventors: Akella V. S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas
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Patent number: 6509197Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.Type: GrantFiled: August 25, 2000Date of Patent: January 21, 2003Assignee: KLA-Tencor CorporationInventors: Akella V. S. Satya, Robert Thomas Long, Lynda C. Mantalas, Gustavo A. Pinto, Neil Richardson
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Publication number: 20020187582Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.Type: ApplicationFiled: June 21, 2002Publication date: December 12, 2002Applicant: KLA-Tencor CorporationInventors: Akella V. S. Satya, Robert Thomas Long, Lynda C. Mantalas, Gustavo A. Pinto, Neil Richardson
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Patent number: 6445199Abstract: Disclosed is a method of inspecting a sample. The sample is illuminated with an incident beam, thereby causing voltage contrast within structures present on the sample. Voltage contrast is detected within the structures. Information from the detected voltage contrast is stored, and position data concerning the location of features corresponding to at least a portion of the stored voltage contrast information is also stored. In a specific embodiment, the features represent electrical defects present on the sample. In another embodiment, the stored position data is in the form of a two dimensional map. In another aspect, the sample is re-inspected and the stored position data is used in analyzing data resulting from the re-inspection.Type: GrantFiled: August 25, 2000Date of Patent: September 3, 2002Assignee: KLA-Tencor CorporationInventors: Akella V. S. Satya, Brian C. Leslie, Gustavo A. Pinto, Robert Thomas Long, Neil Richardson, Bin-Ming Benjamin Tsai
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Patent number: 6433561Abstract: Disclosed is a method of inspecting a sample. At least a portion of the sample is illuminated. Signals received from the illuminated portion are detected, and the detected signals are processed to find defects present on the sample. The processing of the detected signals is optimized, at least in part, based upon results obtained from voltage contrast testing. In one implementation, the illumination is an optical illumination. In another embodiment, the processing comprises automated defect classification, and setup of the automated classification is optimized using the results obtained from voltage contrast testing. In another implementation, the results relate to a probability that a feature present on the sample represents an electrical defect.Type: GrantFiled: August 25, 2000Date of Patent: August 13, 2002Assignee: KLA-Tencor CorporationInventors: Akella V. S. Satya, Gustavo A. Pinto, Robert Thomas Long, Bin-Ming Benjamin Tsai, Brian C. Leslie