Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: A system for wireless power transmission, preferably including one or more power transmitters, detectors, and/or processing modules, and optionally including one or more power receivers and/or auxiliary sensors. A method for field detection, preferably including transmitting power, receiving latent scattering signals, analyzing the scattering signals, and/or acting based on the analysis.

Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: An implantable connector, implantable lead assemblies, and implantable lead assembly kits are provided. The connector comprises an electrically insulative receptacle having a port configured for receiving an electrical lead body portion that carries an electrical terminal, and an electrical spring clip contact mounted within the receptacle. The electrical contact includes a collar and opposing lever arms. The collar is configured for being placed between an expanded state for receiving the terminal therein when the lead body portion is received within the port, and a collapsed state to firmly engage the terminal. The opposing lever arms are configured for being displaced using a tool to correspondingly place the collar between the expanded state and the collapsed state. The implantable connector can be incorporated into a lead and used to receive another lead to form the lead assembly. A tool can be provided with the connector to provide the lead assembly kit.

Abstract: An implantable connector, implantable lead assemblies, and implantable lead assembly kits are provided. The connector comprises an electrically insulative receptacle having a port configured for receiving an electrical lead body portion that carries an electrical terminal, and an electrical spring clip contact mounted within the receptacle. The electrical contact includes a collar and opposing lever arms. The collar is configured for being placed between an expanded state for receiving the terminal therein when the lead body portion is received within the port, and a collapsed state to firmly engage the terminal. The opposing lever arms are configured for being displaced using a tool to correspondingly place the collar between the expanded state and the collapsed state. The implantable connector can be incorporated into a lead and used to receive another lead to form the lead assembly. A tool can be provided with the connector to provide the lead assembly kit.

Abstract: An exemplary capacitor has a capacitor stack positioned in a case with a conductor positioned between the case and a lid. In one embodiment the conductor is positioned between the lid and an upper rim of the case and is welded to the lid and case. In one aspect, a capacitor constructed with round wire connectors for interconnecting anode and cathode layers. In one aspect, a configuration for electrically connecting a terminal wire to a capacitor case in which an end of the wire is attached to the case in end-on fashion. The terminal wire may have an expanded end for attaching to the capacitor case in a manner that minimizes the effect on the height profile of the case.

Abstract: A connector includes a unitary body defining a hollow center region configured and arranged to receive a proximal contact portion of a lead. The unitary body may define connector pockets and seal features within the hollow center region. The connector pockets can be spaced-apart and may define openings through the unitary body. The seal features may be disposed between the connector pockets.

Abstract: Implantable defibrillators are implanted into the chests of patients prone to suffering ventricular fibrillation, a potentially fatal heart condition. A critical component in these devices is an aluminum electrolytic capacitor, which stores and delivers life-saving bursts of electric charge to a fibrillating heart. To reduce capacitor size, manufacturers have developed special aluminum foils, such as core-etched and tunnel-etched aluminum foils. Unfortunately, core-etched foils don't work well in multiple-anode capacitors, and tunnel-etched foils are brittle and tend to break when making some common types of capacitors. Accordingly, the inventors devised a new foil structure having perforations and cavities. In an exemplary embodiment, each perforation and cavity has a cross-sectional area, with the perforations having a larger, for example, 2 to 100 times larger, average cross-sectional area than the cavities.

Abstract: One aspect provides a capacitor feedthrough assembly having an electrically conductive member dimensioned to extend at least partially through a feedthrough hole of a case of the capacitor, the conductive member having a passage therethrough.

Abstract: An embodiment of a modular electronic enclosure is provided as including a chassis having a first portion defining a first compartment, and a second portion defining a second compartment. First and second replaceable units are replaceably received within the first and second compartments, respectively. The modular electronic enclosure also has a fan unit that is replaceably received within a compartment defined by the first portion or the second portion. The fan unit is configured to pull in cooling air through the first portion and exhaust pressurized cooling air through the second portion. A method of cooling a modular electronic enclosure defining first and second compartments is also provided.

Abstract: An exemplary capacitor has a capacitor stack positioned in a case with a conductor positioned between the case and a lid. In one embodiment the conductor is positioned between the lid and an upper rim of the case and is welded to the lid and case. In one aspect, a capacitor constructed with round wire connectors for interconnecting anode and cathode layers. In one aspect, a configuration for electrically connecting a terminal wire to a capacitor case in which an end of the wire is attached to the case in end-on fashion. The terminal wire may have an expanded end for attaching to the capacitor case in a manner that minimizes the effect on the height profile of the case.

Abstract: Implantable defibrillators are implanted into the chests of patients prone to suffering ventricular fibrillation, a potentially fatal heart condition. A critical component in these devices is an aluminum electrolytic capacitors, which stores and delivers one or more life-saving bursts of electric charge to a fibrillating heart. These capacitors make up about one third the total size of the defibrillators. Unfortunately, conventional manufacturers of these capacitors have paid little or no attention to reducing the size of these capacitors through improved capacitor packaging. Accordingly, the inventors contravened several conventional manufacturing principles and practices to devise unique space-saving packaging that allows dramatic size reduction.

Abstract: An embodiment of a modular electronic enclosure is provided as including a chassis having a first portion defining a first compartment, and a second portion defining a second compartment. First and second replaceable units are replaceably received within the first and second compartments, respectively. The modular electronic enclosure also has a fan unit that is replaceably received within a compartment defined by the first portion or the second portion. The fan unit is configured to pull in cooling air through the first portion and exhaust pressurized cooling air through the second portion. A method of cooling a modular electronic enclosure defining first and second compartments is also provided.

Abstract: In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.