Patents by Inventor Robert Trahan

Robert Trahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fuse configuration with modified capacitor border layout for a semiconductor storage device
    Patent number: 6803301
    Abstract: A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element, or isolating layer, for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter. By employing this modified capacitor layout, the fuse element, or isolating layer, will never come into contact with an edge of the first electrode, and thus eliminate a high electric field region from the fuse layout and reliability issues of the prior art fuse configurations. A method for forming the fuse configuration is also provided.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: October 12, 2004
    Assignee: Infineon Technologies Richmond, LP
    Inventors: Ulrich Zimmerman, Allen Chu, Robert Trahan
  • Fuse configuration with modified capacitor border layout for a semiconductor storage device
    Publication number: 20030234435
    Abstract: A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element, or isolating layer, for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter. By employing this modified capacitor layout, the fuse element, or isolating layer, will never come into contact with an edge of the first electrode, and thus eliminate a high electric field region from the fuse layout and reliability issues of the prior art fuse configurations. A method for forming the fuse configuration is also provided.
    Type: Application
    Filed: June 19, 2002
    Publication date: December 25, 2003
    Applicant: Infineon Technologies Richmond, LP
    Inventors: Ulrich Zimmerman, Allen Chu, Robert Trahan