Abstract: A circuit board assembly includes a circuit board and an electrical connector having a connector housing holding contacts in a contact array. The connector housing has a mating end configured to be mated with a mating electrical connector in a mating direction. The electrical connector has cables terminated to the contacts and extending from a cable end. A connector mount is used to locate the electrical connector relative to the circuit board. A bracket is coupled to the mounting surface of the circuit board. A biasing member is coupled to the bracket and the mounting feature and is compressible along a compression axis parallel to the mating direction to allow the electrical connector to float in the mating direction relative to the circuit board.

Abstract: A circuit board assembly includes an electrical connector mounted to a circuit board having a connector housing holding contacts in a contact array. A connector mount having a bracket is coupled to the mounting surface of the circuit board proximate to the mating edge. The electrical connector is movably coupled to the connector mount to move relative to the circuit board during mating with the mating electrical connector. The connector mount has a biasing member compressible along a compression axis parallel to the mating direction to allow the electrical connector to float in the mating direction relative to the circuit board. The electrical connector is movably coupled to the connector mount in a confined envelope in at least one floating direction perpendicular to the mating direction.

Abstract: An electrical connector includes wafer assemblies coupled to a housing. Each wafer assembly includes a leadframe, a wafer body holding the leadframe, and a ground frame coupled to the wafer body to provide electrical shielding for the leadframe. Each leadframe has signal contacts with mating ends extending from the wafer body for mating with mating signal contacts of a mating electrical connector. The mating ends are twisted 45° to define twisted mating interfaces. Each ground frame has ground shields extending from a ground plate along the mating ends of the signal contacts. The ground shields are twisted 45° relative to the ground plate to define twisted shield zones along the mating ends of the signal contacts.

Abstract: A method of fusing 2D and 3D imaging data includes receiving 3D imaging data and 2D color imaging data of a region of interest, segmenting the 3D imaging data to identify anatomical features in the region of interest, including surfaces of the anatomical features and a corresponding volume of the anatomical features, and generating an image by fusing the 2D color imaging data to the 3D imaging data according to the surfaces, the corresponding volumes, and identities of the anatomical features. In some cases, the 3D imaging data is captured via optical coherence tomography. In some cases, the 2D color imaging data is captured via color microscopy. In some cases, the method further includes rendering a final image at an output plane by casting a ray through the fused 3D imaging data for each pixel and viewpoint of the output image plane for the image.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

Abstract: Novel calcilytic compounds of Formula (I), pharmaceutical compositions, methods of synthesis, and methods of using them are provided.

Abstract: Novel calcilytic compounds of Formula (I), pharmaceutical compositions, methods of synthesis, and methods of using them are provided.

Abstract: Novel calcilytic compounds, pharmaceutical compositions, methods of synthesis and methods of using them are provided.