Patents by Inventor Robert V. Dvorak

Robert V. Dvorak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110031693
    Abstract: A matching-based competitive game is used to reinforce the association, correlation, translation, or equation of values. The values are indicia on the face of the tiles, where each tile has at least two different indicia. These values may be cross-language vocabulary words, geographic entities, arithmetic valuations, or chemical symbols, as examples. The classic game of dominoes provides a single tile for every combination of two values in the value set, including the identity element. Because the mathematical increase in combinations, and thus the size of the tile set, becomes prohibitively large for a reasonably-sized value set, the tile set is reduced, resulting in a group of smaller tile sets, having essentially the same statistical matching capability of a normal domino set. The winner(s) of the game are defined as the first player(s) who complete a predetermined number of matches of the indicia values on their tiles.
    Type: Application
    Filed: April 19, 2009
    Publication date: February 10, 2011
    Inventors: Robert V. Dvorak, Bernadette D. Dvorak
  • Patent number: 4686628
    Abstract: A method and apparatus for testing an electrical device and/or circuit in which the device or circuit is stimulated with a known input signal and in which three or more measurements of the response of the device or circuit to such stimulus are taken and utilized to predict a final value of such response according to a predetermined relationship between such predicted final response and the measured response values. Typically the present invention can predict such final value without waiting for the actual final value of the response to occur.
    Type: Grant
    Filed: July 19, 1984
    Date of Patent: August 11, 1987
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: Keibock Lee, Robert V. Dvorak
  • Patent number: 4523143
    Abstract: A digital comparator for determining whether a digital test signal qualifies as an expected logic level, particularly suited to in-circuit digital testing applications. First and second comparing circuits, each formed by a differential amplifier circuit, receive the test signal, a high threshold signal and a low threshold signal. A control circuit selectively enables and inhibits the two comparing circuits so that only one is operative at any instant depending on the expected level of the test signal. The output terminals of the comparing circuits are connected so that the enabled one of the comparing circuits directly provides a pass/fail indication. A standby circuit allows both comparing circuits simultaneously to be selectively energized or deenergized, and an input buffer circuit permits the selective variation of the input impedance of the comparing circuit on the basis of the type of test being performed.
    Type: Grant
    Filed: June 18, 1982
    Date of Patent: June 11, 1985
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: Robert V. Dvorak