Abstract: Each processor in the system is provided with a processor bus over which access to all storage and peripheral equipments is gained. Each access is performed as an address read or write operation. However, under certain circumstances it is necessary to perform a "read-and-hold" operation when accessing a data word which is to be modified. Typically, entries in the master capability table fall into such a category where the data word, while being modified, must not be accessed by any other processor. In such a read-and-hold operation it is vital that the store accessed is held throughout the period of the read-and-hold operation. This facility is obtained by incorporating parity inverting arrangements in each access unit and each processor so that the parity for a read-and-hold operation is inverted. A failure of the hold facility would be detected by the interrogating processor since a parity failure would be observed at the end of the operation.