Patents by Inventor Robert van der Valk

Robert van der Valk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7006590
    Abstract: A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: February 28, 2006
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Simon Skierszkan, Robert van der Valk
  • Publication number: 20050036599
    Abstract: A telecommunication system comprises a telecommunication network (10, 20) with a number of optionally permanent connections for subscribers who are connected to the network via an optionally permanent telecommunication connection (12). A subscriber herein has access to at least one telecommunication service in the network (10, 20) by means of a telecommunication device (11) coupled to a connection. The telecommunication device is moreover able to establish a connection with a loyalty server (21) which is coupled to the network and which is able to manage a data file (229. A points total per subscriber is at least temporarily recorded in the data file. Communication means (11, 23, 24) are provided to send the points total to the telecommunication device (11) of a subscriber.
    Type: Application
    Filed: November 14, 2001
    Publication date: February 17, 2005
    Applicant: Chiptec International N.V.
    Inventor: Robert Van Der Valk
  • Publication number: 20020001359
    Abstract: A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.
    Type: Application
    Filed: May 29, 2001
    Publication date: January 3, 2002
    Inventors: Simon Skierszkan, Robert van der Valk