Abstract: A method of forming a thermoelectric device may include forming a first pattern of epitaxial thermoelectric elements of a first conductivity type on a surface of a semiconductor substrate. A second pattern of epitaxial thermoelectric elements of a second conductivity type may be formed on the surface of the semiconductor substrate. Moreover, the thermoelectric elements of the first and second patterns may be spaced apart, and the first and second conductivity types may be different. Related structures are also discussed.

Abstract: Large area, uniformly low dislocation density single crystal Ill-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm?2, and a dislocation density standard deviation ratio of less than 25%, and methods of forming same, are disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the Ill-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract: An electronic device structure comprises a substrate layer of semi-insulating AlxGayInzN, a first layer comprising AlxGayInzN, a second layer comprising Alx?Gay?Inz?N, and at least one conductive terminal disposed in or on any of the foregoing layers, with the first and second layers being adapted to form a two dimensional electron gas is provided. A thin (<1000 nm) III-nitride layer is homoepitaxially grown on a native semi-insulating III-V substrate to provide an improved electronic device (e.g., HEMT) structure.

Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Abstract: A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

Abstract: AlxGayInzN, wherein 0?x?1, 0?y?1, 0?z?1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 ?m2 area. The AlxGayInzN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality AlxGayInzN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an AlxGayInzN wafer.

Abstract: The present invention relates to various switching device structures including Schottky diode (10), P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers (16) of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer (14). The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).

Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Abstract: Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm?2, and a dislocation density standard deviation ratio of less than 25%. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract: Large-area, single crystal semi-insulating gallium nitride that is usefully employed to form substrates for fabricating GaN devices for electronic and/or optoelectronic applications. The large-area, semi-insulating gallium nitride is readily formed by doping the growing gallium nitride material during growth thereof with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride.