Abstract: More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to the areas containing configuration and any other user-defined data, both so that they are difficult to discover and so that the erasure of all security bits in a EPROM-based PLD would cause a large number of adjacent user-defined bits to be erased as well, hence making it very difficult to extract useful information from a protected device by reverse engineering. Situating security bits in a different, pseudorandom location within each block of the chip makes them difficult to find and so further inhibits reverse engineering.