Patents by Inventor Robert W. Berry
Robert W. Berry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10571515Abstract: It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.Type: GrantFiled: October 3, 2014Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Diyanesh B. Chinnakkonda, Prasanna Jayaraman, Tony E. Sawan
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Patent number: 9703563Abstract: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.Type: GrantFiled: November 4, 2013Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Anand Haridass, Prasanna Jayaraman
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Patent number: 9395782Abstract: An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.Type: GrantFiled: January 24, 2014Date of Patent: July 19, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert W. Berry, Jr., Michael S. Floyd, Jarom Pena, Ryan J. Pennington, Catherine Sherry
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Patent number: 9164563Abstract: An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.Type: GrantFiled: May 24, 2012Date of Patent: October 20, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert W. Berry, Jr., Michael S. Floyd, Jarom Pena, Ryan J. Pennington, Catherine Sherry
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Patent number: 9117011Abstract: Guardband validation for a device having a critical path monitor involves first applying multiple calibration settings to the monitor during functional operation of the processor, and recording corresponding guardbands which result in reduced timing margin. A desired guardband can later be selected for validation. The calibration settings can be based on delays for a critical path. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller.Type: GrantFiled: February 19, 2013Date of Patent: August 25, 2015Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Alan J. Drake, Michael S. Floyd, Richard L. Willaman
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Patent number: 9087135Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.Type: GrantFiled: September 8, 2014Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Anand Haridass, Prasanna Jayaraman
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Patent number: 9020779Abstract: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.Type: GrantFiled: October 25, 2011Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Anand Haridass, Prasanna Jayaraman
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Publication number: 20150057975Abstract: It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.Type: ApplicationFiled: October 3, 2014Publication date: February 26, 2015Inventors: Robert W. Berry, Jr., Diyanesh B. Chinnakkonda, Prasanna Jayaraman, Tony E. Sawan
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Publication number: 20140379288Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: Robert W. Berry, JR., Anand Haridass, Prasanna Jayaraman
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Patent number: 8855969Abstract: Whether validation of at least one of a plurality of previously validated processors on a first system produced data usable for computing a validation start frequency of an unvalidated processor on a second system is determined. If validation of at least one of the plurality of previously validated processors on the first system produced data usable for validating the unvalidated processor, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency.Type: GrantFiled: June 27, 2011Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Diyanesh B. Chinnakkonda, Prasanna Jayaraman, Tony E. Sawan
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Patent number: 8832513Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.Type: GrantFiled: November 20, 2013Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Robert W. Berry, Anand Haridass, Prasanna Jayaraman
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Patent number: 8826092Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.Type: GrantFiled: October 25, 2011Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Anand Haridass, Prasanna Jayaraman
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Publication number: 20140143596Abstract: An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.Type: ApplicationFiled: January 24, 2014Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Robert W. Berry, JR., Michael S. Floyd, Jarom Pena, Ryan J. Pennington, Catherine Sherry
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Publication number: 20140082335Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.Type: ApplicationFiled: November 20, 2013Publication date: March 20, 2014Applicant: International Business Machines CorporationInventors: Robert W. Berry, JR., Anand Haridass, Prasanna Jayaraman
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Publication number: 20140059327Abstract: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.Type: ApplicationFiled: November 4, 2013Publication date: February 27, 2014Applicant: International Business Machines CorporationInventors: Robert W. Berry, JR., Anand Haridass, Prasanna Jayaraman
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Publication number: 20130318364Abstract: An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert W. Berry, JR., Michael S. Floyd, Jarom Pena, Ryan J. Pennington, Catherine Sherry
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Publication number: 20130103927Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.Type: ApplicationFiled: October 25, 2011Publication date: April 25, 2013Applicant: International Business Machines CorporationInventors: Robert W. Berry, JR., Anand Haridass, Prasanna Jayaraman
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Publication number: 20130103354Abstract: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.Type: ApplicationFiled: October 25, 2011Publication date: April 25, 2013Applicant: International Business Machines CorporationInventors: Robert W. Berry, JR., Anand Haridass, Prasanna Jayaraman
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Patent number: 8347022Abstract: A method comprises providing a golden ROM unit comprising known good ROM code. The golden ROM is coupled to a ROM socket of a target system. The target system is booted, wherein booting comprises providing power to the target system and independently providing power to the ROM socket. The known good ROM code is loaded from the golden ROM to a system memory of the target system. Power is removed from the ROM socket and the golden ROM is decoupled from the ROM socket. A first subject ROM is coupled to the ROM socket. Power is provided to the ROM socket and the first subject ROM is programmed with the known good ROM code.Type: GrantFiled: December 18, 2008Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Robert W. Berry, Michael Criscolo, Michael T. Saunders
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Publication number: 20120330616Abstract: A frequency guard band validation unit can determine whether at least one of a plurality of previously validated processors was validated on a first system having a substantially similar configuration as a second system in which an unvalidated processor is being tested. If at least one of the plurality of previously validated processors was validated on the first system, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency. This can reduce the overall validation cycle time.Type: ApplicationFiled: June 27, 2011Publication date: December 27, 2012Applicant: International Business Machines CorporationInventors: Robert W. Berry, Diyanesh B. Chinnakkonda, Prasanna Jayaraman, Tony E. Sawan