Patents by Inventor Robert W. Bower
Robert W. Bower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11257973Abstract: A method for passing photovoltaic current between a subcell formed from a single crystal Group ll-VI semiconductor material and a subcell formed from a single crystal Group IV semiconductor material, includes the steps of forming a first subcell by an epitaxial growth process, the first subcell having a first upper surface; forming a tunnel heterojunction between the first subcell and the second subcell, and tunneling carriers formed by light incident on the first and second subcells through the tunnel heterojunction, thereby permitting a photoelectric series current to flow through the first and second subcells.Type: GrantFiled: July 1, 2019Date of Patent: February 22, 2022Assignee: EPIR Technologies, Inc.Inventors: Sivalingam Sivananthan, Michael Carmody, Robert W. Bower, Shubhrangshu Mallick, James Garland
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Patent number: 11108903Abstract: A Light Floatable Structure is attached to the footprint of a Mobile Electronic Device when near an area where the device might be dropped accidentally into water or other similar liquid where the device might sink. The attached Light Floatable Structure provides the buoyancy needed to prevent the Mobile Electronic Device and attached Light Floatable Structure from sinking. The dimensions and shape of this This Light Floatable Structure are confined to the length and width of the footprint of the Mobile Electronic Device to preserve its feel and adheres to the Mobile Electronic Device with an interface that allows easy attachment and removal of the Light Floatable Structures from the Mobile Electronic Devices when desired.Type: GrantFiled: October 26, 2017Date of Patent: August 31, 2021Inventors: Robert W. Bower, Wei D. Bower, Michael S. Bower
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Publication number: 20200135955Abstract: A photovoltaic cell comprises a first subcell formed of a Group IV semiconductor material, a second subcell formed of a Group II-VI semiconductor material, and a tunnel heterojunction interposed between the first and second subcells. A first side of the tunnel heterojunction is formed by a first layer that is adjacent to a top surface of the first subcell. The first layer is of a first conductivity type, is comprised of a highly doped Group IV semiconductor material. The other side of the tunnel heterojunction is formed by a second layer that adjoins the lower surface of the second subcell. The second layer is of a second conductivity type opposite the first conductivity type, and is comprised of a highly doped Group II-VI semiconductor material. The tunnel heterojunction permits photoelectric series current to flow through the subcells.Type: ApplicationFiled: July 1, 2019Publication date: April 30, 2020Applicant: EPIR Technologies, IncInventors: Sivalingam SIVANANTHAN, Michael CARMODY, Robert W. BOWER, Shubhrangshu MALLICK, James GRALAND
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Patent number: 10340405Abstract: A photovoltaic cell comprises a first subcell formed of a Group IV semiconductor material, a second subcell formed of a Group II-VI semiconductor material, and a tunnel heterojunction interposed between the first and second subcells. A first side of the tunnel heterojunction is formed by a first layer that is adjacent to a top surface of the first subcell. The first layer is of a first conductivity type, is comprised of a highly doped Group IV semiconductor material. The other side of the tunnel heterojunction is formed by a second layer that adjoins the lower surface of the second subcell. The second layer is of a second conductivity type opposite the first conductivity type, and is comprised of a highly doped Group II-VI semiconductor material. The tunnel heterojunction permits photoelectric series current to flow through the subcells.Type: GrantFiled: December 10, 2009Date of Patent: July 2, 2019Assignee: EPIR Technologies, Inc.Inventors: Sivalingam Sivananthan, Michael Carmody, Robert W. Bower, Shubhrangshu Mallick, James Garland
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Publication number: 20180115638Abstract: A Light Floatable Structure is attached to the footprint of a Mobile Electronic Device when near an area where the device might be dropped accidentally into water or other similar liquid where the device might sink. The attached Light Floatable Structure provides the buoyancy needed to prevent the Mobile Electronic Device and attached Light Floatable Structure from sinking. The dimensions and shape of this This Light Floatable Structure are confined to the length and width of the footprint of the Mobile Electronic Device to preserve its feel and adheres to the Mobile Electronic Device with an interface that allows easy attachment and removal of the Light Floatable Structures from the Mobile Electronic Devices when desired.Type: ApplicationFiled: October 26, 2017Publication date: April 26, 2018Inventors: Robert W. Bower, Wei D. Bower, Michael S. Bower
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Patent number: 9455364Abstract: A photovoltaic cell comprises a first subcell formed of a Group IV semiconductor material, a second subcell formed of a Group II-VI semiconductor material, and a tunnel homojunction interposed between the first and second subcells. A first side of the tunnel homojunction is formed by a first layer that is adjacent to a top surface of the first subcell. The first layer is of a first conductivity type and is comprised of a highly doped Group IV semiconductor material. The other side of the tunnel homojunction is formed by a second layer that adjoins the lower surface of the second subcell. The second layer is of a second conductivity type opposite the first conductivity type and also is comprised of a highly doped Group IV semiconductor material. The tunnel homojunction permits photoelectric series current to flow through the subcells.Type: GrantFiled: January 6, 2010Date of Patent: September 27, 2016Assignee: EPIR Technologies, Inc.Inventors: Sivalingam Sivananthan, Michael Carmody, Robert W. Bower, Shubhrangshu Mallick, James Garland
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Publication number: 20110162697Abstract: A photovoltaic cell comprises a first subcell formed of a Group IV semiconductor material, a second subcell formed of a Group II-VI semiconductor material, and a tunnel homojunction interposed between the first and second subcells. A first side of the tunnel homojunction is formed by a first layer that is adjacent to a top surface of the first subcell. The first layer is of a first conductivity type and is comprised of a highly doped Group IV semiconductor material. The other side of the tunnel homojunction is formed by a second layer that adjoins the lower surface of the second subcell. The second layer is of a second conductivity type opposite the first conductivity type and also is comprised of a highly doped Group IV semiconductor material. The tunnel homojunction permits photoelectric series current to flow through the subcells.Type: ApplicationFiled: January 6, 2010Publication date: July 7, 2011Applicant: EPIR Technologies, Inc.Inventors: Sivalingam SIVANANTHAN, Michael CARMODY, Robert W. BOWER, Shubhrangshu MALLICK, James GARLAND
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Publication number: 20110139227Abstract: A photovoltaic cell comprises a first subcell formed of a Group IV semiconductor material, a second subcell formed of a Group II-VI semiconductor material, and a tunnel heterojunction interposed between the first and second subcells. A first side of the tunnel heterojunction is formed by a first layer that is adjacent to a top surface of the first subcell. The first layer is of a first conductivity type, is comprised of a highly doped Group IV semiconductor material. The other side of the tunnel heterojunction is formed by a second layer that adjoins the lower surface of the second subcell. The second layer is of a second conductivity type opposite the first conductivity type, and is comprised of a highly doped Group II-VI semiconductor material. The tunnel heterojunction permits photoelectric series current to flow through the subcells.Type: ApplicationFiled: December 10, 2009Publication date: June 16, 2011Applicant: EPIR TECHNOLOGIES, INC.Inventors: Sivalingam SIVANANTHAN, Michael CARMODY, Robert W. BOWER, Shubhrangshu MALLICK, James GARLAND
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Publication number: 20110024876Abstract: Expungement ions, preferably including hydrogen ions, are implanted into a face of a first, preferably silicon, substrate such that there will be a maximum concentration of the expungement ions at a predetermined depth from the face. Subsequently a monocrystalline Group II-VI semiconductor layer, or two or more such layers, is/are grown on the face, as by means of molecular beam epitaxy. After this a second, preselected substrate is attached to an upper face of the Group II-VI layer(s). Next, the implanted expungement ions are used to expunge most of the first substrate from a remnant thereof, from the grown II-VI layer, and from the second substrate.Type: ApplicationFiled: July 31, 2009Publication date: February 3, 2011Applicant: EPIR TECHNOLOGIES, INC.Inventors: Robert W. BOWER, Sivalingam SIVANANTHAN, James W. GARLAND
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Patent number: 7586115Abstract: Structures and methods to inject electrons into an insulator from a semiconductor layer that are then collected in a thin layer of a direct semiconductor material which in turn emits light by bandgap recombination.Type: GrantFiled: July 3, 2006Date of Patent: September 8, 2009Assignee: EPIR Technologies, Inc.Inventor: Robert W. Bower
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Patent number: 7094667Abstract: A method for producing wafer splitting from ion implantation into silicon after low temperature direct bonding with surface roughness that is ˜1 nm (RMS). This result is an order of magnitude smoother than the previous work (˜10 nm RMS). The key improvement in this work is the use of a low temperature bond resulting in a strong bond before the material is cut. The smooth as-split surfaces produced using a low temperature bond are very important for creation of very thin (<50 nm) silicon-on-insulator (SOI), three-dimensional bonded structures and nanostructures that are split after processing.Type: GrantFiled: May 5, 2003Date of Patent: August 22, 2006Inventor: Robert W. Bower
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Patent number: 7061006Abstract: Structures and methods to inject electrons into an insulator from a semiconductor layer that are then collected in a thin layer of a direct semiconductor material which in turn emits light by bandgap recombination.Type: GrantFiled: December 28, 2001Date of Patent: June 13, 2006Inventor: Robert W. Bower
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Publication number: 20040229443Abstract: Structures, materials and methods for resolving forward implantation skew in the transposed splitting of ion cut materials. By way of example a “material X” is described, such as in the form of a wafer or substrate, having a low resistivity device layer within which nanodevices can be fabricated, an insulation layer, a hydrogen getter layer (e.g., heavily doped region), and a diffusion layer. Devices fabricated in the device layer can be transferred by bonding the surface of the device layer to a target material and then injecting and diffusing hydrogen from the backside of material X through the diffusion layer to the hydrogen getter layer to form a weakened plane. A splitting process then separates the device layer from the remainder of the substrate. A method is also described for thermally isolating a device layer stack, or other target, from a heated diffusion layer when diffusing hydrogen to form the weakened plane.Type: ApplicationFiled: January 21, 2004Publication date: November 18, 2004Inventor: Robert W. Bower
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Patent number: 6812547Abstract: A method for the transposed splitting of ion cut materials. Acceptor centers are formed and selectively introduced into a solid material. In addition, atoms are introduced into the solid material at a location that is offset spatially from acceptor centers. The atoms introduced into the solid material are then transported to the location of the acceptor centers where they will then condense in the region of the acceptor centers. As a result, then any expunged layer that is formed by ion splitting as result of the atoms being introduced into the solid material will follow the contour of the location of the acceptor centers, and will thus be transposed from the initial location of the atoms introduced into the solid material.Type: GrantFiled: January 17, 2002Date of Patent: November 2, 2004Inventor: Robert W. Bower
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Publication number: 20040115899Abstract: A method for the transposed splitting of ion cut materials. Acceptor centers are formed and selectively introduced into a solid material. In addition, atoms are introduced into the solid material at a location that is offset spatially from acceptor centers. The atoms introduced into the solid material are then transported to the location of the acceptor centers where they will then condense in the region of the acceptor centers. As a result, then any expunged layer that is formed by ion splitting as result of the atoms being introduced into the solid material will follow the contour of the location of the acceptor centers, and will thus be transposed from the initial location of the atoms introduced into the solid material.Type: ApplicationFiled: January 17, 2002Publication date: June 17, 2004Inventor: Robert W. Bower
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Patent number: 6346458Abstract: A method for the transposed splitting of ion cut materials. Acceptor centers are formed and selectively introduced into a solid material. In addition, atoms are introduced into the solid material at a location that is offset spatially from acceptor centers. The atoms introduced into the solid material are then transported to the location of the acceptor centers where they will then condense in the region of the acceptor centers. As a result, then any expunged layer that is formed by ion splitting as result of the atoms being introduced into the solid material will follow the contour of the location of the acceptor centers, and will thus be transposed from the initial location of the atoms ;introduced into the solid material.Type: GrantFiled: December 30, 1999Date of Patent: February 12, 2002Inventor: Robert W. Bower
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Patent number: 5503704Abstract: A process for direct bonding similar or dissimilar materials at low temperatures in which a material surface is rendered hydrophilic and reactive by creating nitrogen based radicals on the surface, the surface is direct bonded to a second surface, and the bonded surfaces are annealed at a temperature below approximately 500.degree. C. A nitrogen based constituent is combined with an activator to render the surface hydrophilic and reactive through ammonia plasma activation or activation by use of hydrofluoric acid.Type: GrantFiled: June 8, 1994Date of Patent: April 2, 1996Assignee: The Regents of the University of CaliforniaInventors: Robert W. Bower, Mohd S. Ismail, Brian E. Roberds
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Patent number: 5294760Abstract: A micromachined pressure switch and method of fabrication from silicon wafers using aligned fusion bonding. Pattern etched thermally grown silicon dioxide insulating pads are used to determine the size of silicon pressure membranes on an upper silicon wafer, with the desired switch gap set by the oxide thickness. The silicon membranes are formed by controlled thinning the upper silicon wafers. V-shaped vent grooves are pattern etched into a bottom silicon wafer to form electrodes to which the insulating pads are fusion bonded. The area between the electrodes and the membrane forms wells of specified sizes into which the membranes deflect upon application of pressure. The pressure switch operates when the membrane is deflected to contact the electrodes in the bottom wafer, and closes at the desired pressure threshold for both directions of pressure change with negligible hysteresis. The method of fabrication applies to a single element pressure switch as well as to an array of pressure switches.Type: GrantFiled: June 23, 1992Date of Patent: March 15, 1994Assignee: The Regents of the University of CaliforniaInventors: Robert W. Bower, Mohd S. Ismail
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Patent number: 5236118Abstract: A process for precision alignment and bonding of complementary micromechanical, electrical and optical structures. Surface features of the structures are critically aligned and brought into physical contact within atomic dimensions to form direct bonds without the use of adhesives. The bonds are initially formed at room temperature and then strengthened by a high temperature anneal. Three dimensional structures may be formed in separate prefabricated layers rather than monolithically through the use of this process.Type: GrantFiled: May 12, 1992Date of Patent: August 17, 1993Assignee: The Regents of the University of CaliforniaInventors: Robert W. Bower, Mohd S. Ismail
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Patent number: 4803176Abstract: An improved integrated circuit structure is disclosed in which an active device is formed in contiguous portions of a single slot in an integrated circuit structure or substrate. The method of forming the single slot or merged slot device comprises forming a first portion of the slot, constructing at least a part of one element of the active device in this slot portion, and then forming one or more additional slot portions contiguous with the first slot portion, and constructing one or more further elements of the same active device in the additional contiguous slot portion or portions.Type: GrantFiled: August 18, 1986Date of Patent: February 7, 1989Assignee: Advanced Micro Devices, Inc.Inventor: Robert W. Bower