Abstract: A dual-directional parallel processor. The inventive processor (10) includes an array (20) of processing elements (30). Each processing element has a first circuit (31) for inputting and outputting data, a second circuit (32) for inputting and outputting data; and a third circuit (33, 34) for setting the first circuit (31) in an input mode and for setting the second circuit (32) in an output mode in response to a first mode control signal. The third circuit (33, 34) also sets the first circuit (31) in an output mode and the second circuit (32) in an input mode in response to a second mode control signal. In the illustrative embodiment, data is communicated between the first and the second circuits (31, 32) and the processor further includes a fifth circuit (12) for inputting data to the array and a sixth circuit (14) for outputting data from the array.

Abstract: A switch for communicating short control messages and longer data messages. The control and data switch comprises separate resources for control messages and for data messages, while sharing communication links. Each input port of the switch has a separate control message input FIFO buffer and a data message input FIFO buffer. These buffers allow a control message to preempt a data message that is currently in progress over a link. If there are control message words waiting to be transmitted over the link, they are given prior over any data message words that are ready for transmission over the same link. Preemption of an ongoing data message by a control message takes place without disrupting the data message, other than delaying it.