Abstract: A system and method for increasing the performance of read cycles in instrumentation systems having multiple interconnected buses by converting the read cycles into write cycles and taking advantage of the write posting and FIFO buffering capabilities of the bus interface logic between each of the interconnected buses. When a requestor device desires to initiate a read cycle of memory situated on the same or a different bus, the requestor device first creates a data transfer packet containing information about the desired data. The requestor device then generates a write cycle to DMA logic situated near the memory desired to be read. The DMA logic uses the 32 bit address provided from the requestor device, to obtain information about the transfer and then initiates DMA write cycles to perform the desired transfer. Since each bus interface bridge includes write posting capability, the write operation can be performed much more efficiently than a read operation.

Abstract: A modified IEEE 488.1 bus interface increases, by as much as a factor of eight, the rate at which inter-instrument data transfers can be performed. The bus interface state machines presented in the ANSI/IEEE Std 488.1-1987 have been modified so that if all the devices involved in a particular data transfer are equipped to handle high speed data transfers, then a modified data transmission methodology is used so as to enable multiline messages to be transmitted at a higher speed than would otherwise be possible. If any of the devices involved in a particular data transfer does not have an interface equipped to handle high speed data transfers, this condition is automatically detected by the interfaces with high speed capability, and then the standard data transmission methodology is used. The high speed data transmission mode is totally transparent to the controller software in that it does not require any changes to the controller software nor to the device drivers and device application programs.