Patents by Inventor Robert W. Davis
Robert W. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8099273Abstract: A system and method for compressing trace data from an emulation system. Scan chains may receive trace data from configurable logic blocks inside one or more emulation chips, and the data received from the scan chains may be compressed. Where delta compression is used, the scan chains may also perform a delta detection function. Alternatively, delta detection may be performed using the outputs of the scan chains. In addition, event detectors may be implemented within or outside of the scan chains. Compression of the trace data may include receiving a plurality of data sets and performing compression along cross-sections of the combined data sets.Type: GrantFiled: June 5, 2003Date of Patent: January 17, 2012Assignee: Mentor Graphics CorporationInventors: Charley Selvidge, Robert W. Davis, Peer Schmitt, Joshua D. Marantz
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Patent number: 7734423Abstract: A method system, and apparatus for virtual modeling of biological tissue yields virtual multicellular individuals that exhibit adaptive emergent functionality in response to environmental stimuli. Virtual environmental parameters and cells with genomes are generated, and modified by genetic operations. Cells are developed into generations of multicellular individuals, which are evaluated and selected via evolutionary search according to fitness criteria, and individuals exhibiting adaptive emergent functionality, such as self-repair, are developed and identified.Type: GrantFiled: September 23, 2005Date of Patent: June 8, 2010Assignee: Crowley Davis Research, Inc.Inventors: William L. Crowley, Jr., Ullysses A. Eoff, Cap C. Petschulat, Mason E. Vail, Richard D. Newman, Timothy L. Andersen, Timothy Otter, Robert W. Davis
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Patent number: 7185298Abstract: A method and computer program product for parasitic extraction from a previously calculated capacitance solution include steps of: (a) receiving as input a design database for an integrated circuit design; (b) receiving as input a first set of operating conditions and a second set of operating conditions for the integrated circuit design; (c) calculating a first resistance solution and a single capacitance solution from the design database and the first set of operating conditions; (d) performing a parasitic extraction of the first resistance solution and the single capacitance solution to generate a first set of parasitic values; (e) calculating a second resistance solution from the design database and the second set of operating conditions; (f) performing a parasitic extraction of the second resistance solution and the single capacitance solution to generate a second set of parasitic values; and (g) generating as output the first set of parasitic values and the second set of parasitic values.Type: GrantFiled: December 17, 2004Date of Patent: February 27, 2007Assignee: LSI Logic CorporationInventors: John D. Corbeil, Jr., Daniel W. Prevedel, Robert W. Davis
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Patent number: 6880142Abstract: A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.Type: GrantFiled: October 16, 2002Date of Patent: April 12, 2005Assignee: LSI Logic CorporationInventors: Qian Cui, Robert W. Davis, Sandeep Bhutani, Payman Zarkesh-Ha, John D. Corbeil, Jr., Prabhakaran Krishnamurthy
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Patent number: 6871333Abstract: A method of characterizing a total width and an overall effective length for a bent gate. The bent gate is divided into logical portions, and each of the logical portions is designated as one of a bent portion, a corner portion, and a straight portion. A corner portion gate width and a corner portion effective length are computed for each of the logical portions designated as a corner portion. Similarly, a bent portion gate width and a bent portion effective length are computed for each of the logical portions designated as a bent portion. Likewise, a straight portion gate width and a straight portion effective length are computed for each of the logical portions designated as a straight portion. The total width of the bent gate is computed from the corner portion gate width, the bent portion gate width, and the straight portion gate width.Type: GrantFiled: October 7, 2002Date of Patent: March 22, 2005Assignee: LSI Logic CorporationInventors: SangJune Park, Robert W. Davis
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Publication number: 20040249623Abstract: A system and method for compressing trace data from an emulation system. Scan chains may receive trace data from configurable logic blocks inside one or more emulation chips, and the data received from the scan chains may be compressed. Where delta compression is used, the scan chains may also perform a delta detection function. Alternatively, delta detection may be performed using the outputs of the scan chains. In addition, event detectors may be implemented within or outside of the scan chains. Compression of the trace data may include receiving a plurality of data sets and performing compression along cross-sections of the combined data sets.Type: ApplicationFiled: June 5, 2003Publication date: December 9, 2004Inventors: Charley Selvidge, Robert W. Davis, Peer G. Schmitt, Joshua D. Marantz
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Publication number: 20040078765Abstract: A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.Type: ApplicationFiled: October 16, 2002Publication date: April 22, 2004Inventors: Qian Cui, Robert W. Davis, Sandeep Bhutani, Payman Zarkesh-Ha, John D. Corbeil, Prabhakaran Krishnamurthy
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Publication number: 20040068704Abstract: A method of characterizing a total width and an overall effective length for a bent gate. The bent gate is divided into logical portions, and each of the logical portions is designated as one of a bent portion, a corner portion, and a straight portion. A corner portion gate width and a corner portion effective length are computed for each of the logical portions designated as a corner portion. Similarly, a bent portion gate width and a bent portion effective length are computed for each of the logical portions designated as a bent portion. Likewise, a straight portion gate width and a straight portion effective length are computed for each of the logical portions designated as a straight portion. The total width of the bent gate is computed from the corner portion gate width, the bent portion gate width, and the straight portion gate width.Type: ApplicationFiled: October 7, 2002Publication date: April 8, 2004Inventors: SangJune Park, Robert W. Davis
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Patent number: 6600730Abstract: A system for distributing separate multiple satellite communication services signals to receivers at a local earth site on a single cable line. A dual satellite antenna receives the signals from two separate satellites, each of which can correspond to a respective satellite communication service. The received satellite signals are processed into two separate frequency bands. A frequency converter using frequency division multiplexing converts at least one of the received frequency bands so as to position both of the frequency bands adjacent to each other. A summer receives the adjacent frequency bands and distributes them on a single cable line to receivers so that the receivers have access to the separate multiple satellite communication service signals on a single cable line.Type: GrantFiled: August 20, 1998Date of Patent: July 29, 2003Assignee: Hughes Electronics CorporationInventors: Robert W. Davis, Walter R. Kepley, Robert D. Cassagnol, Douglas M. Dillon
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Patent number: 6493851Abstract: A method identifies the cause of poor correlation between an integrated circuit model and measured integrated circuit performance. The method includes determining the propagation delays through two separate integrated circuit components. The propagation delays are then compared to each other to identify the cause of the poor correlation.Type: GrantFiled: May 3, 2001Date of Patent: December 10, 2002Assignee: LSI Logic CorporationInventors: Randall E. Bach, Robert W. Davis
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Patent number: 5783312Abstract: A continuous strip of sheet metal is progressively lanced and then expanded by coining rolls to form an expanded ladder-like reinforcing strip. The strip has laterally extending parallel spaced bars integrally connected on one side by a coined solid spline and on the other side by a coined spline lanced to form slits at longitudinally spaced intervals. The strip is roll-formed into a U-shaped channel which is fed into an extruder head for reinforcing an extruded resilient weatherstrip having a tubular portion projecting from the embedded continuous solid spline and a retaining wall portion reinforced with the embedded lanced spline.Type: GrantFiled: December 19, 1996Date of Patent: July 21, 1998Assignee: The Gem City Engineering Co.Inventors: Kerry L. Laughman, Terry R. Suitts, Daniel J. Davis, Robert W. Davis
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Patent number: 5302466Abstract: A continuous strip of sheet metal is progressively sheared with longitudinally spaced and laterally extending slits to form opposing U-shaped tabs having corresponding edge portions and successively connected by corresponding center portions of the strip. In one embodiment, the sheared strip is fed between first and second overlapping sets of power driven pinch rollers which progressively grip the edge and center portions, respectively, and the second set of pinch wheels is longitudinally offset and driven at a higher peripheral speed to produce precisely uniform expansion of the strip by deforming the U-shaped tabs into V-shaped tabs. A hot melt adhesively impregnated flexible filament is progressively attached to the expanded center portions of the strip while the strip is heated to form a continuous center connection. In another embodiment, the strip of opposing U-shaped tabs is expanded into opposing V-shaped tabs by coining or thinning a connecting center portion of the strip.Type: GrantFiled: February 11, 1993Date of Patent: April 12, 1994Assignee: The Gem City Engineering Co.Inventors: Robert W. Davis, Thomas H. Harney
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Patent number: 5199142Abstract: The opposite edge portions and the center portion of a continuous strip of sheet metal are progressively sheared with longitudinally spaced and laterally extending slits to form opposing U-shaped tabs having corresponding edge portions and successively connected by corresponding center portions of the strip. The sheared strip is fed between first and second overlapping sets of power driven pinch rollers which progressively grip the edge and center portions, respectively, and the second set of pinch wheels is longitudinally offset and driven at a higher peripheral speed to produce precisely uniform expansion of the strip by deforming the U-shaped tabs into V-shaped tabs. A hot melt adhesively impregnated flexible filament is progressively attached to the expanded portions of the strip while the strip is heated, and the expanded strip is progressively formed into a channel which is fed into an extrusion head for producing a reinforced rubber-like weatherstrip.Type: GrantFiled: September 4, 1991Date of Patent: April 6, 1993Assignee: The Gem City Engineering Co.Inventor: Robert W. Davis
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Patent number: 4290664Abstract: A bridge adapter assembly connects a plurality of modular telephone cables and multiple conductor (e.g. twenty-five pair) telephone cables. The bridge adapter assembly includes a housing having first and second generally rectangular major surfaces which are generally parallel to one another, first and second generally rectangular side walls, and first and second generally rectangular end walls. A first multiple contact connector is mounted in an opening in the first side wall, and a second multiple contact connector is mounted in an opening in the second side wall. Modular connector jacks are mounted in openings in the first end wall and the second end wall. Conductors within the housing connect the first and second multiple contact connectors and the modular connector jacks. Since no connectors are provided on either the first or the second major surfaces, a plurality of the bridge adapter assemblies may be stacked to provide a large number of connections.Type: GrantFiled: September 28, 1979Date of Patent: September 22, 1981Assignee: Communications Systems, Inc.Inventors: Robert W. Davis, Paul D. Tracy