Patents by Inventor Robert W. Greene

Robert W. Greene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
    Publication number: 20240128968
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: June 2, 2023
    Publication date: April 18, 2024
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 11671091
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: June 6, 2023
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
    Publication number: 20220021384
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: July 28, 2021
    Publication date: January 20, 2022
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 11082040
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 3, 2021
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
    Publication number: 20200295750
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: April 1, 2020
    Publication date: September 17, 2020
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 10630284
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: April 21, 2020
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
    Publication number: 20190007042
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 3, 2019
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 10050616
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 14, 2018
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 9755615
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 5, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements when Connected Between Terminals
    Publication number: 20170163256
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 9496849
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: November 15, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements when Connected Between Terminals
    Publication number: 20160191039
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: July 30, 2015
    Publication date: June 30, 2016
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Digitally tuned capacitors with tapered and reconfigurable quality factors
    Patent number: 9293262
    Abstract: The present disclosure describes tuning capacitors with tapered and reconfigurable quality factors. Digitally tuned capacitors (DTCs) that provide a variable quality factor (Q) while maintaining a constant or near constant capacitance as well as DTCs that provide one or more Q values in a tapered distribution while maintaining a constant or near constant capacitance are described. The present disclosure also describes DTCs that provide one or more capacitances in a tapered distribution and one or more Q values in a tapered distribution.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: March 22, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Shawn Bawell, Robert Broughton, Peter Bacon, Robert W. Greene, Tero Tapio Ranta
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 9106227
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: August 11, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
    Publication number: 20140312957
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: January 27, 2014
    Publication date: October 23, 2014
    Applicant: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals
    Publication number: 20140312958
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Application
    Filed: February 11, 2014
    Publication date: October 23, 2014
    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 8669804
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: March 11, 2014
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 8638159
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: January 28, 2014
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 8604864
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: December 10, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Digitally Tuned Capacitors with Tapered and Reconfigurable Quality Factors
    Publication number: 20130208396
    Abstract: The present disclosure describes tuning capacitors with tapered and reconfigurable quality factors. Digitally tuned capacitors (DTCs) that provide a variable quality factor (Q) while maintaining a constant or near constant capacitance as well as DTCs that provide one or more Q values in a tapered distribution while maintaining a constant or near constant capacitance are described. The present disclosure also describes DTCs that provide one or more capacitances in a tapered distribution and one or more Q values in a tapered distribution.
    Type: Application
    Filed: August 15, 2012
    Publication date: August 15, 2013
    Inventors: Shawn Bawell, Robert Broughton, Peter Bacon, Robert W. Greene, Tero Tapio Ranta