Abstract: A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requestors. The rows of the table are fetched to assure that requestors having high bias values are granted more frequent access to the shared resource. A look-ahead feature skips rows having all zeros and an unbiased cycle that assures all requesting ports are serviced regardless of their bias values.

Abstract: The present invention is related to methods and systems for providing different stripe sizes for different zones for at least a first of a plurality of mirrored drives to improve data rates. The first drive has a plurality of zones. In one embodiment, a first stripe size is selected for a first zone, and a second stripe size is selected for a second zone. The said second stripe size is different than said first stripe size.

Abstract: The present invention is related to methods and systems for improving the read performance of a drive array, such as a RAID 5 array, having an “n” number of drives so that the read performance is greater than (n−1) times that of an independent single drive. Formatting information for each of at least three drives is received. A first parity block size for use with corresponding first zones of the at least three drives is selected. A second parity block size different than the first parity block size is selected for use with corresponding second zones of the at least three drives. The first and the second parity block sizes are selected to increase the read performance from the drive array based on at least a portion of the formatting information.

Abstract: A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.

Abstract: A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.

Abstract: An encoder accepts an N byte set of values for each of a plurality of image components, with N being greater than one and, for each N byte set of values, identifies a compressed symbol length, K, wherein K is the smallest integer such that the difference between any two adjacent bytes is expressible in K bits or less, outputs an indication of K and outputs a K bit difference between the byte and an immediately prior byte, for each byte in the set.

Abstract: A computer system with a pluggable drive carrier assembly comprises a cabinet and a circuit board disposed within the cabinet. The circuit board, such as a base board, has a number of connectors attached to a first surface. A drive unit such as a hard disk drive is secured within a carrier. A logic connector and a power connector are adapted to attach to the drive. A flexible circuit assembly connects the logic connector and the power connector to a blind plug. The blind plug is adapted to mate with any of the number of connectors. A cam surface and lever arrangement is used to urge into engagement the blind plug and the selected one of the number of connectors. The logic connector and the power connector both have a number of contacts that extend in a direction generally parallel to the first surface of the circuit board such that a backplane is not required and can be eliminated.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: The present invention is related to methods and systems for accessing multimedia data stored on a disk array to ensure that the transfer rate does not fall below a selected minimum transfer rate independent of where the multimedia data is stored on the disk array. In one embodiment, the sizes of blocks accessed are varied and the direction of access is selected to enhance read performance. A plurality of blocks are read whose sizes vary linearly as data is being read from a first disk in a backward direction, from an inner diameter side of the first disk, towards an outer diameter of the first disk. Blocks are read from a second disk in a forward direction, towards an inner diameter of the second disk.

Abstract: The present invention is related to methods and systems for reducing head movements during accesses to drives within a drive array by dynamically selecting which one of a first drive and a second drive is to be used to read data stored within a first logical address range. A first set of data is stored in both the first drive and the second drive. The logical block addresses accessed by at least a portion of read operations are monitored. The first drive is designated as a data source for data stored on both the first drive and the second drive in the first logical address range. The second drive is designated as a data source for data stored on both the first drive and the second drive outside the first logical address range. The designation of drives is performed at least partly in response to the monitoring act.

Abstract: The present invention is related to methods and apparatus that can enhance the reliability of a hard drive by providing a built-in error check in the drive. Conventional hard drives can erroneously seek to an incorrect location on a platter of the hard drive. The erroneous seek corrupts the data stream and is difficult to detect and correct. Embodiments of the present invention can detect a logical block address assigned to a portion of the platter of the hard drive and thereby detect when an erroneous seek has occurred. Upon detection of an error, one embodiment of the present invention can further take corrective action to read from the correct portion of the platter.

Abstract: A computer system with a pluggable drive carrier assembly comprises a cabinet and a circuit board disposed within the cabinet. The circuit board, such as a base board, has a number of connectors attached to a first surface. A drive unit such as a hard disk drive is secured within a carrier. A logic connector and a power connector are adapted to attach to the drive. A flexible circuit assembly connects the logic connector and the power connector to a blind plug. The blind plug is adapted to mate with any of the number of connectors. A cam surface and lever arrangement is used to urge into engagement the blind plug and the selected one of the number of connectors. The logic connector and the power connector both have a number of contacts that extend in a direction generally parallel to the first surface of the circuit board such that a backplane is not required and can be eliminated.

Abstract: A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requesters. The rows of the table are fetched to assure that requesters having high bias values are granted more frequent access to the shared resource.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

Abstract: A method and digital circuit for indicating whether the frequencies of two clocks are within a predetermined range of each other, wherein a first pattern of alternating binary one's and zero's is created using the active edge of the first clock; first and second sampled patterns are generated by sampling the first pattern with respective first and second edges of the second clock; and a first acceptance signal is asserted if either the first or second sampled pattern has alternating binary one's and zero's. A second acceptance signal is asserted as above but interchanging the two clock signals. A near-frequency signal is generated when both acceptance signals are asserted. A clock error signal is the inversion of the near-frequency signal.