Abstract: Devices, apparatus, systems and methods for using an inclined weight bench for supporting free weights, being adjustable and customizable for allowing a weight lifter to work out on their own without a separate spotter. The device can have a multi-step spotters platform, a detachable bench assembly with a backside support frame positioned at 45 degree angle with variable adjustable inclination. The device can have a vertical support post fixed to a lateral ground support and dumbbell support frame having one horizontal beam. The device can have dumbbell cradles having enlarged surface areas that safely support and hold the weights, reinforced angled support braces with two feet members and adjustable seat with pin-locking fasteners. Also, a separate spotter can be used that sits on one of the steps and straddles the backrest to help the lifter raise and lower the free weights when needed.

Abstract: A platform for providing an interface between a host vessel and ship-to-shore craft has a water buoyant surface that is transportable on the host vessel, an angled deck within the surface, an inner and outer ramp, and an inner and outer deck of different deck heights within the platform.

Abstract: A digital processing system comprises a central processing unit (CPU) operating in a virtual address domain for executing both operating system software and user software to perform various processing tasks; a direct memory access (DMA) controller; a memory management unit (MMU) programmed to translate virtual memory addresses to physical memory addresses; and a plurality of memory blocks for storing digital words in registers having physical addresses; wherein the DMA controller is governed by the CPU and is operable in the virtual address domain for controlling a transfer of digital words from a source block of memory to a destination block of memory through the MMU which translates the virtual source and destination memory addresses received from the DMA controller to corresponding source and destination physical addresses of the memory. Also disclosed is a method of operating the digital processing system.

Abstract: An internal memory section of a digital processing system protectable by error detection and correction (EDAC) codes comprises at least one bank of registers for storing digital words and EDAC codes corresponding thereto. An EDAC code is generated for each digital word stored in a register of the at least one bank and the stored digital words of the at least one bank are checked with their EDAC codes. Also disclosed is a method of accessing digital words protectable by EDAC codes in a digital processing system which comprises the steps of: storing digital words and EDAC codes corresponding thereto in at least one bank of registers of an internal memory of the system; generating an EDAC code for each digital word upon storage; reading digital words and their corresponding EDAC codes from designated registers of the at least one bank; and checking the read digital words with their EDAC codes.

Abstract: Apparatus embedded in a processor system comprises: an auxiliary instruction queue (IQ); and control circuits for governing the programming of registers of the auxiliary IQ with a set of instructions and for controlling insertion of the programmed instructions of the auxiliary IQ into an instruction execution stream of the processor system substantially without interrupting processing operations thereof. In another embodiment, the IQ is memory mapped to render it part of the memory space of the processor system and the control circuits govern the programming of the auxiliary IQ with a set of debug instructions accessed from a debug monitor program over the bus. In yet another embodiment, each storage register of the IQ is fabricated in the IC to survive an upset transient wherein a monitor circuit detects an onset of the upset transient and governs the control circuits to transfer data of selected registers of the processor system into the auxiliary IQ for storage during the upset transient.

Abstract: A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and generating an output signal representative thereof; a multiple vote circuit governed by the output signals of the registers for generating an output signal of the logic cell; and a circuit coupled to each latching register for altering selectively the scan chain data signal input thereto. A scan chain test system for and method of testing at least one multiple voted logic cell of the aforementioned type are also disclosed.

Abstract: A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; and an arbiter circuit for regulating access of said control devices to the system resource. Each control device includes a throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.

Abstract: A memory management unit (MMU) of a digital processing system operating in a virtual address domain and a physical address domain comprises a memory programmable to store translation mappings between virtual addresses and physical addresses of the processing system. The memory is also programmable to store control codes representative of EDAC protection corresponding to the translation mappings. A method of operating the memory management unit (MMU) comprises the steps of: programming a memory of the MMU with virtual to physical address translation mappings; and programming the memory of the MMU with control codes representative of EDAC protection corresponding to the translation mappings.

Abstract: A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated at an output of the storage cell. The storage cell comprises at least three data capturing circuits, each operable to capture and store a time sample of the data input signal at each predetermined time interval, the stored data sample of each circuit being generated correspondingly at an output thereof. Coupled to the outputs of the data capturing circuits is a circuit for generating a signal representative of a stored data sample selected from at least two of the circuit outputs. Also coupled to the data capturing circuits is a circuit for causing each data capturing circuit to capture a different time sample of the input data signal from the other data capturing circuits over each predetermined time interval.

Abstract: A heater control for controlling operation of a heater switch (12) in an evaporative cooler having an alternative heater mode in which a heater element (40) is energized and part of the air flow is blanketed by a shutter (37) controlled by a slide (24) or other operator. The slide (24) has a cam face (25) which directly or indirectly compresses a spring (22) as the shutter (41) is closed, the spring (22) otherwise biasing the heater switch (12) to its open contact state, but when the spring (22) is compressed, the switch (12) reverts to its closed contact state to energize the heater element (40).

Abstract: Salinity control of sump water in an evaporative cooler (10) wherein a pump (19) continuously impels a water flow from a sump (11) to an evaporative surface where some of the water is evaporated by air flow from a fan (15, 16). Control is affected by sensing electrical resistance of the sump water with monel probes (36) energised with low voltage alternating current, and initiating an "ON" period of a timer (quad NOR gate) when resistance drops below a preset level. During the "ON" period a solenoid valve (25) is opened in a bleed line and some only of the pumped sump water is passed to drain, without interruption of cooler operation.