Abstract: The depth of a cavity or chamber (10') is measured by using the chamber as the resonator of an electronic oscillator (24) whose oscillations are coupled to fluid in the cavity by transducers (12, 13). Both the variable-depth main chamber (10') and a reference chamber (117) of fixed depth are measured. Variations in the data obtained from the chambers are caused by factors affecting the velocity of propagation of sound in the fluid. An accurate measurement of the depth of the main chamber is obtained by compensating direct data (at 42) obtained from the main chamber (10'), using, data (at 43) obtained from the fixed-depth reference chamber (117). In one embodiment an inertance orifice (121) is utilized between the two chambers. The fluid inertance of the orifice, together with the compliance of the fluid in the main chamber (10'), form a resonant system whose anti-resonant frequency is a measure of the dimensions of the main chamber. (Inertance is the acoustical equivalent of inductance.

Abstract: A cavity such as a chamber (10) of a hydraulic cylinder (2) containing a movable piston (4) is equipped with transducers (12) for transmitting alternating pressure signals into a fluid in the chamber and for receiving signals from it. The fluid chamber acts as a resonant tank circuit for determining the frequency of an external electronic oscillator (24). The frequency of oscillation of the circuit indicates the depth of the cavity, i.e., the position of the piston in the cylinder. Multiple modes of oscillation are employed (34, 36) in the same chamber to provide high accuracy and resolution of ambiguities. In one embodiment chambers (10', 66) on both sides of the piston (4') of a double-acting cylinder (2') are measured, and the readings are combined (76) to reduce errors that would otherwise result from changes in temperature, pressure, viscosity and other parameters unrelated to the position of the piston.

Abstract: MOMOM structural geometry and fabrication techniques are disclosed. A first oxidizable metal strip (3) and a second coplanar nonoxidizable metal strip (6) are deposited on an insulating substrate (2). An insulating layer (12) is deposited on the metal strips, followed by deposition of a third nonoxidizable metal layer. A generally vertical notch (14) is cut through the layers to the substrate providing left and right sections (15, 16) of the third metal layer, left and right sections (19, 20) of the insulating layer, and the first and second metal layers with facing edges (23, 24) spaced by the notch therebetween. An oxidized tip (25) is formed at the facing edge of the first metal layer. A fourth metal layer (26) is ballistically deposited over the oxidized tip and the left section of the third metal layer, using the notch edge of the right section of the third metal layer as a shadow mask, followed by oxidization of the fourth metal layer.

Abstract: MOMOM structural geometry and fabrication techniques are is disclosed. First and second metal layer strips (6 and 10) are supported on an insulating substrate (4) and have vertically overlapped portions sandwiched between insulating layers (8, 12). A generally vertical side (18) is defined through the layers to the substrate to expose vertical edges (20, 24) of the metal layers which are oxidized (32, 34) and covered by a third metal layer (44) extending therebetween. In the preferred embodiment, the middle insulating layer (8) is undercut (28), oxidized (36, 40), and filled with metallization (50), to provide a vertical rectilinear conduction path.

Abstract: A power JFET (2) has a stack (4) of alternating conductivity type layers (5-9) forming a plurality of channels (6, 8). The JFET has an ON state conducting bidirectional current horizontally through the channels. The channels are stacked vertically, and the JFET has an OFF state blocking current flow through the channels due to vertical depletion pinch-off. Various main and gate terminal and drift region structures are disclosed.

Abstract: MOMOM structural geometry and fabrication techniques are disclosed. First and second metal layer strips (6 and 10) are supported on an insulating substrate (4) and have vertically overlapped portions sandwiched between insulating layers (8, 12). A generally vertical side (18) is defined through the layers to the substrate to expose vertical edges (20, 24) of the metal layers which are oxidized (32, 34) and covered by a third metal layer (44) extending therebetween. In the preferred embodiment, the middle insulating layer (8) is undercut (28), oxidized (36, 40), and filled with metallization (50), to provide a vertical rectilinear conduction path.

Abstract: A power JFET (2) has a common drift region (4) between split first and second longitudinally separated sets of rows (6, 8) of alternating conductivity type layers (10-20 and 21-31) forming a plurality of channels (11, 13, 15, 17, 19, 22, 24, 26, 28 and 30). The JFET has an ON state conducting bidirectional current horizontally longitudinally through the common drift region and the channels. The JFET has an OFF state blocking current flow through the channels due to horizontally lateral depletion pinch-off. The layers of the rows extend vertically and horizontally longitudinally such that the direction of layering extends horizontally laterally. Particular gate structure is disclosed.

Abstract: MOMOM structural geometry and fabrication techniques are disclosed. A first oxidizable metal strip (3) and a second coplanar nonoxidizable metal strip (6) are deposited on an insulating substrate (2). An insulating layer (12) is deposited on the metal strips, followed by deposition of a third nonoxidizable metal layer. A generally vertical notch (14) is cut through the layers to the substrate providing left and right sections (15, 16) of the third metal layer, left and right sections (19, 20) of the insulating layer, and the first and second metal layers with facing edges (23, 24) spaced by the notch therebetween. An oxidized tip (25) is formed at the facing edge of the first metal layer. A fourth metal layer (26) is ballistically deposited over the oxidized tip and the left section of the third metal layer, using the notch edge of the right section of the third metal layer as a shadow mask, followed by oxidization of the fourth metal layer.

Abstract: A power JFET (2) has a common drift region (4) between a pair of spaced first and second stacks (6, 8) of alternating conductivity type layers (10-14 and 15-19) forming a plurality of channels (11, 13, 16 and 18). The JFET has an ON state conducting bidirectional current horizontally through the common drift region and the channels. The channels are stacked vertically, and the JFET has an OFF state blocking current flow through the channels due to vertical depletion pinch-off. Field shaping and high blocking voltage capability are provided. Particular main terminal and gate structure is disclosed.

Abstract: A solid display is provided by a semiconductor switched between transparent and opaque conditions according to external removal of carriers from the conduction band for controlling absorption of light-energy. A semiconductor has an energy band gap affording a normally saturated conduction band in response to impinging light energy of a given range wavelength. The normally saturated condition of the semiconductor prevents further absorption, and enables light to pass thererthrough. The semiconductor is switched to an opaque condition by completing an electric circuit for removing carriers from the conduction band to enable further absorption of incident light in the semiconductor by raising additional carriers from the valence band to the conduction band.

Abstract: A lateral bidirectional power FET (2) has a common drift region (6) between first and second stacks (8, 10) of alternating conductivity type layers (12-17 and 18-23). A notch (38) extends vertically downwardly into the drift region and laterally separates the stacks above the drift region. The stacks include a plurality of channel-containing regions (12-14 and 18-20) interleaved with a plurality of source regions (15-17 and 21-23). In the ON state, bidirectional current flows serially through the source regions and channels of each stack and through the drift region. In the OFF state, voltage is dropped across the plurality of junctions in series in the stacks, and the respective junctions with the drift region.

Abstract: Lateral planar FET structure (2) is disclosed for bidirection power switching, including AC application. Voltage blocking capability is enhanced in the lateral current flow device (2) by field shaping in the drift region (22). In the OFF state, the field shaping region (24) straightens field lines and prevents gradient induced depletion and unwanted inversion of conductivity type along a lateral drift region portion (54) extending beneath a top major surface (28) of the substrate between channel-containing regions (6) and (8).

Abstract: Lateral FET structure is disclosed for bidirectional power switching, including AC application. A notch extends downwardly from a top major surface to separate left and right source regions and left and right channel regions, and direct the drift region current path between the channels around the bottom of the notch. Split gate electrodes in the notch proximate the channels control bidirectional conduction, and are at non-common potentials in the OFF state to increase breakdown voltage. Self-shielding of the gates is also disclosed to further increase OFF state breakdown voltage.

Abstract: An AC solar cell is provided by a pair of PN junction type solar cells connected in antiparallel between a pair of main terminals, and means for directing light alternatingly on the PN junctions to generate an alternating potential across the main terminals. AC electrical energy is generated without a DC to AC converter.

Abstract: Lateral FET structure is disclosed for bidirectional power switching, including AC application. Integral avalanche protection is provided by a pair of isolation regions forming protective barrier junctions with a common layer, which junctions are in parallel with the reverse blocking junctions of the power FET in the OFF state and have a lower reverse breakover threshold for protecting the latter. A plurality of integrated FETs each have left and right source regions and left and right channel regions with a common drift region therebetween, and conduct current in either direction according to the polarity of main terminals.

Abstract: Lateral FET structure is disclosed for bidirectional power switching. A split gate structure is provided to prevent unwanted formation of potential conduction channels in the OFF state of the FET. This enables the gate to be referenced in common to one of the source regions in the OFF state while still affording high blocking voltage capability. A multicell matrix array is also disclosed.

Abstract: Lateral FET structure is disclosed for bi-directional power switching. A raised gate structure enables distal gate electrode portions to be in close proximity to FET channels and the remainder of the gate to be separated from the drift or drain region by a substantially greater distance so as to prevent undesired inducement of potential conduction channels through the drift region in the OFF state. This enables the gate to be referenced to the same potential level as one of the main terminals in the OFF state while still affording high voltage blocking capability. A multicell matrix array is also disclosed.

Abstract: Lateral FET structure is disclosed for bidirectional power switching, including AC appliction. Main electrodes extend downwardly into and through respective source regions and at least into regions having respective channel portions. Notch gate structure extends into the drift region and separates the main electrodes and the respective source regions and channels. High density, high voltage plural FET structure is disclosed.

Abstract: Lateral FET structure is disclosed for bidirectional power switching, including AC application. Voltage blocking capability is substantially increased by a shielding electrode insulated between first and second gate electrodes in a notch between laterally spaced source regions and channel regions joined by a common drift region around the bottom of the notch. The shielding electrode prevents the electric field gradient toward the gate electrode on one side of the notch from inducing depletion in the drift region along the opposite side of the notch. This prevents unwanted inducement of conduction channels in the drift region during the OFF state of the FET. High density, high voltage, plural FET structure is disclosed.

Abstract: Lateral FET Structure is disclosed for bidirectional power switching, including AC application. A pair of notches, each with a gate electrode, extend downwardly from a top major surface to separate left and right source regions and left and right channel regions, and direct the drift region current path between the channels around the bottoms of the notches. In the OFF state, each gate electrode shields its respective notch edge drift region portion from the electric field gradient from the other gate electrode, to prevent depletion along the notches and unwanted inducement of conduction channels, thus affording higher OFF state voltage blocking capability. High density, high voltage plural FET structure is disclosed.