Abstract: A method and apparatus for routing packets through a multiport switch involves attaching indicators to packets before the packets are passed through a switch fabric, and then using the indicators to look-up output port vectors after the packets have been passed through the switch fabric. In a preferred embodiment of a 64.times.64 port switch, an 8-bit output channel vector and a 15-bit output port index are attached to a packet and passed through the switch fabric. The 8-bit output channel vector directs the packet to the proper output packet processor(s) and the 15-bit output port index is used to look-up an output port vector that identifies the output port(s) that will receive the packet. The method and system provide low packet overhead and flexible scaling.

Abstract: A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.