Abstract: A circuit for, and method of, detecting a signal level on a node and a mobile telephone device incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a switch coupled between a voltage source and the node, (2) a pulse generator coupled to the switch and configured to generate a pulse to control the switch and (3) a detection circuit coupled to the node and configured to detect a signal level at the node on closure of the switch.

Abstract: A method and apparatus for selecting and mixing electronic signals. The circuit has an operational amplifier and two or more ganged, tapped-resistors in which the tap divides the resistance into a first and a second resistance. The tapped-resistors are connected so that either the first or the second resistance provides the effective input resistance for that signal at the operational amplifier. The second resistance of one of the tapped-resistors provides the output resistance for all signals at operational amplifier. As the tapped resistors are equivalent and their taps ganged, when the signals are mixed, those signals whose effective input resistance at the operational amplifier is selected to be the second resistance have unit gain, while those signals whose effective input resistance at the operational amplifier is selected to be the first resistance have a gain equal to the second resistance divide by the first resistance.

Abstract: An amplifier architecture wherein a primary or main operational amplifier is combined with a secondary or auxiliary high power operational amplifier to maintain the charge on a large load capacitor which operates as voltage reference source for a high precision analog circuit module. The auxiliary amplifier is activated only during brief periods for which a very high slew rate is required. This is achieved by additionally including a control circuit which regulates the operation of the auxiliary amplifier so that it operates only during very short intervals of very high load while the main operational amplifier accommodates all other normal operating conditions.

Abstract: A bandgap voltage reference circuit for 0.35-.mu.m, 3-volt CMOS technology operates in an essentially temperature independent manner and having low supply voltages. The bandgap voltage reference circuit incorporates two operational amplifiers. One operational amplifier biases bipolar devices of the circuit and generates a PTAT voltage across a resistor, and the other operational amplifier buffers a voltage related to the PTAT voltage and a voltage across one bipolar device to generate the bandgap voltage reference. In one embodiment, the circuit includes a start-up circuit to ensure a stable and desired start-up state. A current bias may also be provided. The bandgap voltage reference of the second operational amplifier may also provide a regulated supply for the first stage of the circuit. The second operational amplifier also provides a buffered output to a resistor divider circuit to supply a voltage divider to generate voltages below the 1.24-volt bandgap voltage.

Abstract: Testing of digital-to-analog converters is accelerated by applying one or more different approaches. One approach relies on a switched capacitor, which lowers the overall capacitance of the converter during testing, thereby reducing the settling time for each code value. Another approach makes the duration of each testing step a function of the particular code value, rather than using the worst-case settling time for each testing step. Yet another approach uses a sequence of non-consecutive code values to determine whether each switch in the converter is functional. Using non-consecutive code values permits the use of partial settling times during converter testing. Each of the approaches can be used to accelerate the testing of D/A converters, whether they have linear or folded resistor strings.

Abstract: A device comprises: an analog-to-digital converter; a digital signal processor; a digital dither signal generator; and a signal coupling device adapted to selectively couple one of the dither signal generator and the digital signal processor to the signal path in the converter. A method of testing a dithered analog-to-digital converter employing an M-bit digital signal generator, M being a positive integer, comprises the steps of: generating an M-bit, periodic signal; providing the generated signal to the dithered converter at a point along the signal path of the dithered converter in place of the dither signal; and measuring the digital output signal produced by the converter.

Abstract: A circuit which detects the median peak of a burst of pulses. The peak value of each pulse in a pulse burst is detected and stored. The peak value of each pulse is then compared to the peak value of every other pulse and the results of the comparison are used to determined the median peak.

Abstract: A voltage controlled crystal oscillator circuit, such as a Pierce oscillator circuit, includes an amplifier and is balanced by the addition of another varactor connected directly to the amplifier, whereby the frequency pull range is increased. Further, greater linearity can be achieved by adding another pair of varactors to the circuit.