Abstract: Methods and systems for managing and/or processing a blockchain to maintain data security for confidential and/or personal data are provided. According to certain aspects, the disclosed data security techniques may enable access sharing functionality utilizing the blockchain. For example, access sharing may be utilized to file documents, share policy information, and/or comply with an audit. The data security techniques disclosed herein also enable the use of smart contracts to transfer funds associated with payment obligations and/or other forms of blockchain based payments, comply with anti-money laundering requirements, report industry data, validate interest payments and/or maintain agent sales data. Data security may be achieved through the use of public key/private key encryption techniques.

Abstract: Methods and systems for managing and/or processing a blockchain to maintain data security for confidential and/or personal data are provided. According to certain aspects, the disclosed data security techniques may enable access sharing functionality utilizing the blockchain. For example, access sharing may be utilized to share policy information. The policy information may be associated with a smart contract. Accordingly, the policy information may be encrypted using a public key for the smart contract and compiled into a block of the blockchain. In response to a request to provide access to the information to a particular node, the private key for the smart contract may be encrypted using the public key for the particular node and compiled into a block of the blockchain.

Abstract: Methods and systems for processing a blockchain comprising a plurality of immutable sales records corresponding to sales made by agents of an entity are provided. According to certain aspects, a transaction request indicating a sale made by an agent of the entity may be received at a first node. A block including a sales record indicating the sale made by the agent may be added to a blockchain and transmitted to another node for validation. The first node may add the block to a copy of the blockchain, where the block may be identified by a hash value that references a previous block in the blockchain that includes at least one additional sales record.

Abstract: Methods and systems for managing and/or processing a blockchain to maintain data security for confidential and/or personal data are provided. According to certain aspects, the disclosed data security techniques may enable access sharing functionality utilizing the blockchain. For example, access sharing may be utilized to file documents, share policy information, and/or comply with an audit. The data security techniques disclosed herein also enable the use of smart contracts to transfer funds associated with payment obligations and/or other forms of blockchain based payments, comply with anti-money laundering requirements, report industry data, validate interest payments and/or maintain agent sales data. Data security may be achieved through the use of public key/private key encryption techniques.

Abstract: In the disclosed methods, integrated circuit (IC) dice are manufactured from a common specification, and the IC dice are tested for defective circuitry. Respective defect sets are generated to indicate defective circuitry in the IC die. The dice are assigned to bins based on the respective defect sets. For each bin, all IC dice assigned to the bin have equivalent respective defect sets. Product definitions are provided, and each product definition indicates a respective set of circuitry required for a corresponding product. Respective sets of packages are manufactured for each product. In the manufacturing of each package of a respective set of packages for each product, one or more IC dice are selected from a subset of the plurality of bins such that the IC dice have respective defect sets allowed by the product definition of the product. The selected IC dice are then manufactured into the package.

Abstract: A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

Abstract: A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

Abstract: Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics.” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

Abstract: Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.

Abstract: Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.

Abstract: Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.

Abstract: Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Abstract: Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Abstract: Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Abstract: FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

Abstract: Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

Abstract: Described are methods and circuits for accurately placing signal transitions, or “edges,” simultaneously on two or more pins of an integrated circuit (IC). A conventional tester is connected to an integrated circuit, such as a programmable logic device. The integrated circuit is adapted to include a coincidence detector that compares the timing of edges on two input pins of the integrated circuit. The coincidence detector indicates when the two edges are coincident, allowing an operator of the tester to adjust the tester to establish coincidence. The amount of offset necessary to provide coincident edges is stored in a database for later use in deskewing edges used in subsequent tests. The integrated circuit can be a programmable logic device configured to include one or more coincidence detectors with which to place edges relative to one another on different pins.

Abstract: FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.