Patents by Inventor Robert Wadsworth

Robert Wadsworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test mode circuitry for a programmable tamper detection circuit
    Patent number: 8827165
    Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: David C. McClure, Sooping Saw, Robert Wadsworth
  • Test mode circuitry for a programmable tamper detection circuit
    Patent number: 7978095
    Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: July 12, 2011
    Assignee: STMicroelectronics, Inc.
    Inventors: David C. McClure, Sooping Saw, Robert Wadsworth
  • TEST MODE CIRCUITRY FOR A PROGRAMMABLE TAMPER DETECTION CIRCUIT
    Publication number: 20110148620
    Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.
    Type: Application
    Filed: March 3, 2011
    Publication date: June 23, 2011
    Applicant: STMICROELECTRONICS, INC.
    Inventors: David C. McClure, Sooping Saw, Robert Wadsworth
  • Test mode circuitry for a programmable tamper detection circuit
    Publication number: 20070115122
    Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.
    Type: Application
    Filed: June 23, 2006
    Publication date: May 24, 2007
    Inventors: David McClure, Sooping Saw, Robert Wadsworth