Abstract: The present invention relates to a method of forming a graphene-containing laminate, the method comprising: providing a first graphene layer structure on a substrate; forming a first metal oxide layer on the graphene layer structure by depositing and then oxidising a layer of metal; forming a second metal oxide layer on the first metal oxide layer; and forming a second graphene layer structure on the second metal oxide layer by CVD.

Abstract: There is provided a graphene sensor, preferably a graphene biosensor, comprising: a graphene layer structure provided on a non-metallic surface of a substrate, the graphene layer structure having an exposed, functionalised sample surface for receiving a sample for testing; first and second electrical contacts provided in contact with the graphene layer structure, and arranged on opposite sides of the functionalised sample surface; wherein each electrical contact is separated from the functionalised sample surface by an adjacent metal oxide layer, and wherein each electrical contact and adjacent metal oxide layer are capped with a passivating layer, whereby a sample for testing applied to the sample surface cannot contact the electrical contacts; and wherein the functionalised sample surface is devoid of photoresist.

Abstract: There is provided a transistor comprising: a graphene layer structure provided on a non-metallic surface of a substrate, the graphene layer structure having an insulating cap; a source contact provided in contact with a first edge of the graphene layer structure; an insulator provided in contact with an opposite, second edge of the graphene layer structure; a drain contact provided in contact with the insulator, whereby there is a distance of least separation between the drain contact and the graphene layer structure along the second edge of the graphene layer structure and through the insulator; and a gate contact provided (i) over the graphene layer structure and separated therefrom by the insulating cap and/or (ii) under the graphene layer structure and separated therefrom by substrate.

Abstract: Methods of providing an air- and/or moisture-barrier coating on at least a portion of a two-dimensional material are described. In particular, the methods provide an improved approach for providing a doped two-dimensional material, preferably graphene, on a substrate wherein at least a portion of the two-dimensional material is coated with an air- and/or moisture-barrier coating that comprises an inorganic oxide, fluoride or sulfide. Two-dimensional materials provided with an air- and/or moisture impermeable inorganic oxide, fluoride or sulfide coating and an electronic device comprising the same are also described.

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

Abstract: The present invention provides a method for the production of an electronic device, the method comprising: (i) providing a substrate comprising first and second layers on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have a constant separation from the substrate, (ii) supplying a flow comprising a precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form a graphene layer structure on a surface of the first layer of the substrate, wherein the inlets are cooled to less than 100° C. and the susceptor is heated to a temperature of at least 50° C.

Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

Abstract: The present invention provides method for forming a diode, the method comprises providing a first graphene layer structure on a first substrate; providing a second graphene layer structure on a second substrate; treating the first graphene layer structure with an oxidant to form a graphene oxide surface thereon; and aligning the second graphene layer structure against the graphene oxide surface of the first graphene layer structure.

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

Abstract: According to a first aspect of the disclosure, an integrated frequency multiplier circuit is provided. The circuit comprises a substrate, a strip of graphene, first and second electrode, a dielectric layer, a frequency input electrode, and a frequency output electrode. The strip of graphene has a uniform width provided on the substrate, the strip having a width x and a length y extending from a first end to a second end. The first and second electrodes are provided in electrical contact with the strip of graphene at the first and second ends of the strip of graphene respectively. The dielectric layer is provided on the strip of graphene, wherein the dielectric layer is provided across the width x of the strip of graphene. The frequency input electrode is formed on the dielectric layer, wherein the frequency input electrode is provided across the width x of the strip of graphene.

Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

Abstract: The present invention provides a method for the production of a polymer-coated graphene layer structure, the method comprising: providing a substrate on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have a constant separation from the substrate, supplying a flow comprising a precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form a graphene layer structure on the substrate, wherein the inlets are cooled to less than 100° C. and the susceptor is heated to a temperature of at least 50° C.

Abstract: There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n?1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

Abstract: Methods of providing an air- and/or moisture-barrier coating on at least a portion of a two-dimensional material are described. In particular, the methods provide an improved approach for providing a doped two-dimensional material, preferably graphene, on a substrate wherein at least a portion of the two-dimensional material is coated with an air- and/or moisture-barrier coating that comprises an inorganic oxide, fluoride or sulfide. Two-dimensional materials provided with an air- and/or moisture impermeable inorganic oxide, fluoride or sulfide coating and an electronic device comprising the same are also described.

Abstract: An embodiment of the invention may include a method, computer program product and computer system for profile picture selection. The method, computer program product and computer system may include a computing device which may classify user photographs in user account data into one or more photograph classifications. The computing device may classify an emotion conveyed by a media interaction by the user and select a classified user photograph matching the emotion conveyed by the media interaction by the user. The computing device may display selected user photograph with the media interaction by the user.

Abstract: An embodiment of the invention may include a method, computer program product and computer system for profile picture selection. The method, computer program product and computer system may include a computing device which may classify user photographs in user account data into one or more photograph classifications. The computing device may classify an emotion conveyed by a media interaction by the user and select a classified user photograph matching the emotion conveyed by the media interaction by the user. The computing device may display selected user photograph with the media interaction by the user.

Abstract: The present invention is directed to cytokines and genes that are differentially affected by TNF blockers and the use of these genes and cytokines to help asses the TB risks of new immunosuppressive therapies, to help evaluate the effects of new TB vaccines, and to help assess TB susceptibility in persons exposed to Mycobacterium tuberculosis.