Patents by Inventor Robert Walter Dmitroca

Robert Walter Dmitroca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6993578
    Abstract: The inventive mechanism manages packet delay values that a network incurs in transported data packets. The mechanism uses a plurality of bins for maintaining the number of times that delay values fall within the range of a particular bin. The mechanism also uses a storage array for maintaining delay values that do not fall with the range of the bins. For each delay value that is received, the mechanism determines whether the delay value falls within the bin range. If so, the mechanism increments the number of a particular bin into which the delay value falls within. If not, the mechanism stores the delay value in the storage array and effectively doubles the size of the range of the bins. The mechanism will then effectively re-slot the values into the scaled bins. This allows for the numbers in the bins to used to form graphs detailing the latency of the network for display to a user.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: January 31, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Robert Walter Dmitroca
  • Patent number: 6072343
    Abstract: The inventive mechanism is included with each module in a chain of modules. The inventive mechanism includes a clock mechanism which is edge synchronous among all of the clock mechanisms in the other modules, meaning that each clock has the same frequency and zero phase delay with respect to the clocks of the other modules. The clock mechanism of the first module of the chain is the master, the subsequent clocks are slaves. The inventive mechanism includes a trigger mechanism which allows each module of the chain to initiate a trigger event. The trigger mechanism is tied to the clock mechanism, so that the trigger signal is sent out on the next rising edge of the clock. Since each module is tied to the same clock frequency and has zero delay, when one module sends out a trigger, the remaining modules will detect the trigger on the next clock cycle, and the trigger event will begin simultaneously in all modules.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: June 6, 2000
    Assignee: Hewlett-Packard Company
    Inventor: Robert Walter Dmitroca