Patents by Inventor Robert Washburn

Robert Washburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210315384
    Abstract: A seat includes a seat surface having a periphery and a carrier overmolded onto the seat surface over the periphery. The carrier has a periphery and a frame is overmolded onto the carrier over the carrier periphery. The seat is assembled without fasteners. A method for making the seat includes overmolding a carrier onto a periphery of a seat surface to form a seat surface/carrier assembly, tensioning the seat surface/carrier assembly in a mold and overmolding a frame onto a periphery of the seat surface/carrier assembly.
    Type: Application
    Filed: August 1, 2019
    Publication date: October 14, 2021
    Inventors: Craig Martin Oomen, Randy James Sayers, Robert A. Bratty, Kelly Washburn, Michael Long, Michael Stanton
  • Publication number: 20210291709
    Abstract: A vehicle seat includes a support structure, a seat surface (14) and a molded polymeric frame (18). The frame has an edge region and the seat surface (14) is mounted to the frame (18) and the frame is mounted to the support structure. At least a portion of the edge region is flexible.
    Type: Application
    Filed: August 1, 2019
    Publication date: September 23, 2021
    Inventors: Craig Martin Oomen, Samuel Smith, Manfred Mueller, Michael Long, Kelly Washburn, Robert A. Bratty
  • Patent number: 8872081
    Abstract: A relative navigation system projects a grid into space from a grid generator and an object, such as an unmanned aerial vehicle, may use the projected grid to aid in the landing of the object. Methods of adjusting the projected grid including stabilizing the projected grid and orienting the grid generator relative to the earth.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: October 28, 2014
    Assignee: GE Aviation Systems LLC
    Inventors: Michael Steven Feldmann, Frank Saggio, III, John Robert Washburn
  • Publication number: 20130107219
    Abstract: A relative navigation system projects a grid into space from a grid generator and an object, such as an unmanned aerial vehicle, may use the projected grid to aid in the landing of the object. Methods of adjusting the projected grid including stabilizing the projected grid and orienting the grid generator relative to the earth.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Applicant: GE AVIATION SYSTEMS LLC
    Inventors: Michael Steven Feldmann, Frank Saggio, III, John Robert Washburn
  • Publication number: 20090300912
    Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.
    Type: Application
    Filed: August 17, 2009
    Publication date: December 10, 2009
    Inventors: John Thomas, Russell Rapport, Robert Washburn
  • Patent number: 7579971
    Abstract: The present invention is a digital to analog converter circuit that provides significantly lower distortion than achieved by digital to analog converter circuits having comparable speed and resolution utilizing the present art. The present invention provides linear or higher order transitions between clock transition time points rather than step transitions used in the present art. Distortion reduction can exceed 30 dB in the embodiment with linear sample-to-sample transitions and greater in alternate embodiments with non-linear transitions. In other embodiments, the present invention can provide low distortion at resolutions from 16 to 24 bits or more at sample rates typical of high-speed 8-bit devices of the present art.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: August 25, 2009
    Inventors: Robert Washburn, Robert F. McClanahan
  • Patent number: 7576995
    Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: August 18, 2009
    Assignee: Entorian Technologies, LP
    Inventors: John Thomas, Russell Rapport, Robert Washburn
  • Patent number: 7508723
    Abstract: A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 24, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Paul Goodwin, Brian Miller, Robert Washburn
  • Publication number: 20080291747
    Abstract: A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Applicant: STAKTEK GROUP L.P.
    Inventors: Paul Goodwin, Brian Miller, Robert Washburn
  • Patent number: 7405634
    Abstract: An improved method and apparatus for altering the effective electrical length of trace on a circuit board. In the present invention small tabs of etch are routed perpendicular to the trace in the unused areas between adjacent traces. In an embodiment of the invention, a method of tuning the delay characteristics of a transmission line is implemented by inserting compensation tabs into the unused area between the segments of adjacent straight traces or a serpentine run. Utilizing the method and apparatus of the present invention, it is possible to achieve significantly greater electrical length for an electrical trace without introducing coupling problems or utilizing large amounts of space on a circuit board.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: July 29, 2008
    Assignee: Dell Products L.P.
    Inventors: James B. Mobley, Robert Washburn
  • Publication number: 20070194813
    Abstract: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.
    Type: Application
    Filed: November 7, 2006
    Publication date: August 23, 2007
    Inventors: Robert Washburn, Robert McClanahan
  • Publication number: 20070183228
    Abstract: The present system is an electronic circuit designed for incorporation on high-speed computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.
    Type: Application
    Filed: October 26, 2006
    Publication date: August 9, 2007
    Inventors: Robert Washburn, Robert McClanahan
  • Publication number: 20070130760
    Abstract: A duct for containing a cable and method for mounting the cable therein include providing the duct with a collapsible or flexible wall movable between a contracted condition for mounting the duct in a conduit and an extended condition of increased cross-sectional area for inserting a cable in the duct. The duct is moved to its extended condition by an applied internal pressure and, after the cable has been inserted, the duct is returned to its contracted condition. The duct has a multiple layer construction: an inner layer, an outer protective layer and a reinforcing layer between them. There may be frictional reducing ribs on the inner and/or outer layer in order to reduce the forces necessary to place the duct and/or the cable. Alternatively, the duct may have a single, thin layer.
    Type: Application
    Filed: February 26, 2007
    Publication date: June 14, 2007
    Applicant: ARNCO CORPORATION
    Inventor: Robert Washburn
  • Publication number: 20070103877
    Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.
    Type: Application
    Filed: November 4, 2005
    Publication date: May 10, 2007
    Inventors: John Thomas, Russell Rapport, Robert Washburn
  • Publication number: 20060294437
    Abstract: The invention is a point-of-load power conditioning system for computer memory modules that provides regulation and fast transient response for memory integrated circuit bias voltages. The invention uses low voltage drop regulation circuitry that is physically located on individual memory modules. Power consumption and memory module regulator power dissipation are minimized by use of off-module power preconditioning that provides module input power at an optimized voltage for the on-module regulator circuitry.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 28, 2006
    Applicant: Thunder Creative Technologies, Inc.
    Inventors: Robert Washburn, Robert McClanahan
  • Publication number: 20060285417
    Abstract: The invention is a clock interface circuit for high-speed computer memory modules. It provides improved timing margin due to improved rise and fall times than achieved with present JEDEC specified clock distribution and timing networks. The invention also provides for improved clock and inverse clock symmetry around VREF.
    Type: Application
    Filed: May 24, 2006
    Publication date: December 21, 2006
    Applicant: THUNDER CREATIVE TECHNOLOGIES, INC.
    Inventors: Robert Washburn, Robert McClanahan
  • Publication number: 20060280004
    Abstract: The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 14, 2006
    Applicant: THUNDER CREATIVE TECHNOLOGIES, INC.
    Inventors: Robert Washburn, Robert McClanahan
  • Publication number: 20060044894
    Abstract: The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.
    Type: Application
    Filed: August 17, 2005
    Publication date: March 2, 2006
    Inventors: Robert Washburn, Robert McClanahan
  • Publication number: 20050189980
    Abstract: The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment, the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system.
    Type: Application
    Filed: April 21, 2005
    Publication date: September 1, 2005
    Inventors: Robert Washburn, Robert McClanahan
  • Publication number: 20050170691
    Abstract: An improved method and apparatus for altering the effective electrical length of trace on a circuit board. In the present invention small tabs of etch are routed perpendicular to the trace in the unused areas between adjacent traces. In an embodiment of the invention, a method of tuning the delay characteristics of a transmission line is implemented by inserting compensation tabs into the unused area between the segments of adjacent straight traces or a serpentine run. Utilizing the method and apparatus of the present invention, it is possible to achieve significantly greater electrical length for an electrical trace without introducing coupling problems or utilizing large amounts of space on a circuit board.
    Type: Application
    Filed: January 30, 2004
    Publication date: August 4, 2005
    Inventors: James Mobley, Robert Washburn