Abstract: A lift truck (10) has a pair of wheel assemblies (21) each of which is rotatable about a pivot point (24) relative to the chassis (12) of the truck through at least 90 degrees between a forward mode and a sideward mode. The wheel (18,20) of each assembly is laterally offset from the assembly's pivot point (24), causing the wheel to describe an arcuate path over the ground as it transitions between the forward and sideward modes. During the transition, an actuator acts on each wheel assembly (21) to pivot the assembly about the pivot point (24), while drive is applied to the wheel to positively drive the wheel along the arcuate patch at a speed that matches the pivotal rotation caused by the actuator. This positive drive imparted to the wheels (18,20) during the transition prevents the truck from rolling if it is located on a slope during the change in orientation of the wheel assemblies (21).

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the system comprises one or more hard disk drive integrated circuit chips residing on a board and a hard disk drive power plug receptacle residing on the board having two different value power supply ports associated therewith. The receptacle is operable to receive a power plug therein, wherein when the power plug is inserted therein in a proper orientation the two different value voltages are properly supplied to the one or more hard disk drive integrated circuit chips, and wherein when the power plug is inserted therein in an improper orientation the two different value voltages are switched with respect to their intended values. The system comprises a reverse power plug orientation protection circuit coupled between the hard disk drive power plug receptacle and at least one of the one or more hard disk drive integrated circuit chips.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: An apparatus and method for converting a pulse-width modulation (PWM) signal to an analog voltage signal. A current source is provided to supply electrical charge at a controllable rate to a ramp capacitor which, during successively occurring cycles of the PWM signal, alternatively receives electrical charge from the current source and discharges previously received electrical charge. A first sampling capacitor receives electrical charge from the ramp capacitor to output a feedback voltage to a feedback circuit to adjust the rate of electrical charge supplied by the current source, with the charge transferred to the first sampling capacitor determined in relation to the charge stored on the ramp capacitor over an entire PWM cycle. A second sampling capacitor receives electrical charge from the ramp capacitor to output the analog voltage, with the charge transferred to the second sampling capacitor determined in relation to the duty cycle of the PWM signal.

Abstract: Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT.

Abstract: Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT.