Patents by Inventor Robert Wierzbicki

Robert Wierzbicki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10051764
    Abstract: An electronic equipment chassis in one embodiment comprises a housing having a front portion and a rear portion, at least one row of dual in-line memory modules disposed at one of an upper level and a lower level of the front portion, and a plurality of storage devices arranged in the front portion adjacent the at least one row of dual in-line memory modules. At least a subset of the dual in-line memory modules and the storage devices are configured so as to be removable from the chassis through a vertical plane of the front portion of the housing.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 14, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Ralph C. Frangioso, Jr., Robert Wierzbicki
  • Patent number: 9706687
    Abstract: An electronic equipment chassis in one embodiment comprises a housing having a front portion and a rear portion, first and second rows of cooling modules disposed at respective upper and lower levels of the front portion, and a plurality of storage devices arranged in the front portion between the first and second rows of cooling modules. At least a subset of the cooling modules and the storage devices are configured so as to be removable from the chassis through a vertical plane of the front portion of the housing.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 11, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Ralph C. Frangioso, Jr., Robert Wierzbicki
  • Patent number: 7722359
    Abstract: A connection assembly has a midplane, first midplane connectors and second midplane connectors. The midplane is divided into an airflow section and a connector section by a dividing line. The midplane defines a first side and a second side which faces away from the first side. The airflow section provides airflow passageways connecting spaces on both sides of the midplane. The connector section provides (i) first mounting locations which are confined to the connector section on the first side and (ii) second mounting locations which are confined to the connector section on the second side. The first midplane connectors are arranged to connect to first circuit board modules, and are mounted over the first mounting locations on the first side. The set of second midplane connectors are arranged to connect to second circuit board modules, and are mounted over the second mounting locations on the second side.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: May 25, 2010
    Assignee: EMC Corporation
    Inventors: Ralph C. Frangioso, Jr., Robert Wierzbicki
  • Patent number: 7445457
    Abstract: A midplane has plated through holes (PTHs) which form a first profile and a second profile. The first profile has (i) an overlapping portion which overlaps at least part of the second profile and (ii) a non-overlapping portion which does not overlap any part of the second profile. A first connector mounts to a first side of the midplane over the first profile, and a second connector mounts to a second side of the midplane over the second profile. At least one PTH is a shared PTH which resides in both the first and second profiles and which engages a pin of the first connector and a pin of the second connector. Additionally, at least one PTH is a non-shared PTH which resides in the non-overlapping portion of the first profile and which engages a pin of the first connector without engaging any pins of the second connector.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 4, 2008
    Assignee: EMC Corporation
    Inventors: Ralph C. Frangioso, Jr., Robert Wierzbicki, Michael L. Schillinger
  • Publication number: 20060069927
    Abstract: Several processors have specifications setting forth that each processor be coupled to a separate specified voltage regulator circuit. Instead, a number of specified voltage regulator circuit(s) is coupled to the several processors. The number of voltage regulator circuit(s) is less than the number of processors. The processors and voltage regulator circuit(s) are coupled to a module, and a thermal limit for the module is maintained because the several processors are coupled to the smaller number of voltage regulator circuits.
    Type: Application
    Filed: June 28, 2004
    Publication date: March 30, 2006
    Inventor: Robert Wierzbicki
  • Publication number: 20050289217
    Abstract: A storage solution includes a first enclosure having modules and non-volatile memory, such as hard disk drives. These modules convert file I/O to block I/O. A second enclosure includes second modules and non-volatile memory. These modules are operable to cause the block I/O to be stored on the non-volatile storage in either the first or second enclosure. Thus, the modules that perform block I/O storage can access storage that resides in the file I/O server. In a different arrangement, the storage system has an enclosure having modules and non-volatile memory. One module converts file I/O to block I/O. Another module transfers block I/O to the non-volatile memory. The first and second modules are interconnected via a data bus. Block I/O is transferred between the first module and the second module via the data bus. The data bus crosses a midplane that interconnects the modules. The second module stores data in the enclosure.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Ralph Frangioso, Robert Wierzbicki