Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.

Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.

Abstract: A hierarchical multi-core debugger interface is described that is configured to enable debugging of a multi-core device. In some implementations, a multi-core debugger renders core-specific user interface components with a core-specific visual characteristic in the hierarchical multi-core debugger interface. In other implementations, the multi-core debugger renders core-specific user interface components in core-specific windows in the hierarchical multi-core debugger interface. In still other implementations, the multi-core debugger renders core-specific user interface components in core-specific windows in the hierarchical multi-core debugger interface, where each core-specific window is displayed with a core-specific visual characteristic.

Abstract: Systems, methods, and other embodiments associated with echo cancellation are described. According to one embodiment, an apparatus includes a plurality of first registers configured to respectively store information related to a performance of a processor and a second register in communication with each of the plurality of first registers. The apparatus also includes logic configured to detect a trigger event; and in response to having detected the trigger event, copy the information related to the performance of the processor respectively in the plurality of first registers into the second register.

Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Abstract: Systems and methods related to a memory device are provided. The systems and methods include using at least one driver with predetermined reduced driving capability to drive at least one of the memory elements of the memory device in a reliable detection algorithm. The at least one driver has reduced driving capability compared to a driver used for standard read access. The reliable detection algorithm can include detecting failing memory elements on a respective reading current diverging from an expected or expectable reading current.

Abstract: A memory cell is provided, the memory cell including a first two-terminal memory element; a second two-terminal memory element; a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: A memory cell is provided, the memory cell including a first two-terminal memory element; a second two-terminal memory element; a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.

Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Abstract: Systems, apparatuses, and methods for system and application debugging are described herein. A tested platform may include a debug event monitor in a boundary scan interface that detects a debug event in a process and determines a characteristic associated with the debug event. The debug event monitor may trigger an application debug event or a boundary scan debug event based at least in part on the determined characteristic. Other embodiments may be described and claimed.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: Embodiments of a method and system for compiling code, such as program-generated code, are disclosed herein. The method and system efficiently encode combined range and stride checks. For example, the method and system are operable to encode combined range and stride checks as they occur in a translation of switch statements. The method and system can generate code to perform the range and stride check, and to branch to the case body, if the range and stride checks are successful. The various embodiments may operate to provide an efficient code transformation, better code density, and processing performance. Other embodiments are described and claimed.

Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Abstract: A system for performing code optimization is described which includes an optimizing analyzer within a compiler to generate a first optimizing transformation and a second optimizing transformation and their satisfying conditions for a compiled code. An optimization transformation module is placed within a linker to determine which of the first and second optimizing transformations should be selected when the compiled code is linked with other compiled codes, and to execute the selected one of the first and second optimizing transformations at link-time. A method of performing code optimization is also described.

Abstract: Embodiments of a method and system for compiling code, such as program-generated code, are disclosed herein. The method and system efficiently encode combined range and stride checks. For example, the method and system are operable to encode combined range and stride checks as they occur in a translation of switch statements. The method and system can generate code to perform the range and stride check, and to branch to the case body, if the range and stride checks are successful. The various embodiments may operate to provide an efficient code transformation, better code density, and processing performance. Other embodiments are described and claimed.

Abstract: In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made of the material for forming the floating gate and which is exposed to an oxidizing atmosphere in order to coat the sidewalls. At the same time, other regions of the structure have an insulating oxide layer. At a point in time prior to the action of an oxidizing atmosphere, nitrogen is implanted into the material of the floating gate in a quantity that appreciably reduces the oxidation at the sidewalls thereof.

Abstract: A system for performing code optimization is described which includes an optimizing analyzer within a compiler to generate a first optimizing transformation and a second optimizing transformation and their satisfying conditions for a compiled code. An optimization transformation module is placed within a linker to determine which of the first and second optimizing transformations should be selected when the compiled code is linked with other compiled codes, and to execute the selected one of the first and second optimizing transformations at link-time. A method of performing code optimization is also described.

Abstract: In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made of the material for forming the floating gate and which is exposed to an oxidizing atmosphere in order to coat the sidewalls. At the same time, other regions of the structure have an insulating oxide layer. At a point in time prior to the action of an oxidizing atmosphere, nitrogen is implanted into the material of the floating gate in a quantity that appreciably reduces the oxidation at the sidewalls thereof.

Abstract: A structure is provided for cooling the tail rotor gearbox of a single rotor helicopter having an anti-torque tail rotor mounted to a vertical stabilizer. The gearbox is mounted within the vertical stabilizer inside an air passage passing through the stabilizer. An air inlet is located in the vertical stabilizer on the side thereof opposite the tail rotor. An exhaust orifice is positioned in the vertical stabilizer on the same side of the stabilizer as the tail rotor. In operation the pressure differential over the vertical stabilizer caused by the rotation of the rotor causes ambient air to enter the inlet, pass through the passage, over the gearbox, and exit from the exit orifice thereby cooling the gearbox.