Abstract: A recurring noise filter for removing from a signal noise generated by parasitic coupling from a switching network. The filter contains an input filter, a sampling switch and an output filter. The input filter is a low pass filter which receives a signal containing noise generated by parasitic coupling from a switching network. The sampling switch is connected between the low pass filter and an output filter, with the sampling switch activating in response to the recurring switching of said switching network to sample the signal during the interval at which said noise does not occur within the signal. The output filter removes signals generated by the sampling switch from the sampled signal thereby generating a noise-filtered signal.

Abstract: A method and apparatus are provided for matching the primary and parasitic capacitances of integrated circuit capacitors. The integrated circuit capacitors to be matched in accordance with the present invention can be of different sizes and connected in different circuit topologies. For example, the matching filter can have a differential filter capacitor structure and the reference circuit can have a single-ended filter configuration (or vice versa). The reference circuit to be matched is initially analyzed to identify the ratio of the primary capacitance, Cp, to the parasitic capacitance, Cg. Thereafter, a matching filter is selected with the desired topology and having the same ratio of the primary capacitance, Cp, to the parasitic capacitance, Cg, as the reference circuit (or a desired offset therefrom). A general technique is disclosed for analyzing capacitance circuits to identify the ratio of the primary capacitance, Cp, to the parasitic capacitance, Cg.

Abstract: An integrated circuit includes an oscillator circuit for generating an output signal having a desired frequency. The oscillator circuit includes a capacitive device having a controllable capacitance value responsive to a control signal. A control circuit is connected to the oscillator circuit for controlling the capacitance value so that the oscillator circuit generates the output signal at the desired frequency. The control circuit includes a memory for storing a digital control word and a control signal generating circuit for converting the digital control word into the control signal for the capacitive device. Setting the desired frequency of the output signal is performed internal to the integrated circuit without requiring complex control circuitry for switching among various capacitors.

Abstract: An integrated transconductor circuit has an active load element and two parallel sets of transconductor stages. The active load element provides a high impedance without requiring a large area within the integrated transconductor circuit, and provides linear impedance when the active load devices are biased in the triode region of their respective characteristic curves. The multiple transconductor stages prevent saturation from reducing the dynamic range available at the output of the transconductor circuit. The parallel sets of transconductor stages are used to improve output linearity by reducing the differences between the threshold voltages of the serially-connected transconductor stages.

Abstract: A method and system for a clock driver is described which can buffer an master clock directly, or generate a output clock signal having a balanced duty cycle which is the input clock frequency divided by a predetermined value. When a frequency control input, such as a rate signal, is switched, the clock output makes a glitchless transition from one frequency to the other. The clock driver includes a counter divider circuit with feedback to produce two signals related by a predetermined phase difference. The counter divider circuit employs predetermined logic delays by buffered gating controlled by the master clock, which produces two signals. These two signals act as "enable" control signals such that the timing of their rising and falling edges is arranged to never propagate through the clock divider circuit to become the edges of output clock. The master clock is gated with these two signals to provide two unbalanced signals which are synchronous to the input clock signal.

Abstract: A level shifter circuit which is suitable for use in an integrated circuit converts an input logic signal having a first voltage potential to an output logic signal having a second voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages, the level shifter circuit allows reliable circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having a higher voltage potential, the same voltage potential, or a lower voltage potential. The level shift circuit includes an inverter stage which drives a fully differential output stage, and the fully differential output stage includes two sections. Each section incorporates a fast switching pair of transistors connected in series across an output supply voltage and ground potential which act as an inverter and which provide an output node at the series connection.