Abstract: Apparatus and methods are disclosed that adjust the phase of a read/write clock signal. The read/write clock signal may be used in a data storage apparatus to regulate reading/writing on a data storage media. An apparatus includes an adjustment circuit that adjusts phase of an edge of a read/write clock signal based on the timing of information that is read from a data storage media. Another apparatus includes a servo circuit and a read/write channel circuit. The servo circuit generates a leading edge transition of a servo gate signal in response to a signal indicating that a read/write transducer is approaching a start of a servo wedge. The read/write channel circuit generates a trailing edge transition of the servo gate signal in response to occurrence of a defined time delay following the transducer reading a servo address mark from the servo wedge.

Abstract: Apparatus and methods are disclosed that adjust the phase of a read/write clock signal. The read/write clock signal may be used in a data storage apparatus to regulate reading/writing on a data storage media. An apparatus includes an adjustment circuit that adjusts phase of an edge of a read/write clock signal based on the timing of information that is read from a data storage media. Another apparatus includes a servo circuit and a read/write channel circuit. The servo circuit generates a leading edge transition of a servo gate signal in response to a signal indicating that a read/write transducer is approaching a start of a servo wedge. The read/write channel circuit generates a trailing edge transition of the servo gate signal in response to occurrence of a defined time delay following the transducer reading a servo address mark from the servo wedge.

Abstract: A method and apparatus are provided for performing on-board, in-circuit, and/or wafer level scan-based testing of integrated circuits. With the apparatus and method, one or more sequential storage elements, e.g., flip/flops, are coupled to combinational logic and are configured to have an additional port for receiving a scan mode signal. The scan mode signal sets the sequential storage element into one of two modes of operation: static mode in which the sequential storage element's output does not change on a falling edge of a scan enable signal or a transitional mode in which the sequential storage element's output is permitted to change on the falling edge. With sequential storage elements configured in this manner, a configuration scan is performed to set certain ones of the sequential storage elements into a static mode and other sequential storage elements into a transitional mode. A test pattern is then applied to the sequential storage elements and a pattern capture cycle is commenced.