Patents by Inventor Robert Wiser

Robert Wiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240428850
    Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller which is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
    Type: Application
    Filed: July 15, 2024
    Publication date: December 26, 2024
    Applicant: Ceremorphic, Inc.
    Inventors: Jay A. CHESAVAGE, Robert WISER, Neelam SURANA
  • Patent number: 12131813
    Abstract: A medication dispenser apparatus is described. The apparatus includes a container configured to hold medication, a display interface, and a controller configured to perform, in sequence, a learning operation in which the controller learns a medication dispensing regimen of the container, a validation operation in which the controller validates the learned medication dispensing regimen; and a notification operation in which the controller provides on the display interface a status of use of the container for medication dispensing in relation to the learned medication dispensing regimen.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: October 29, 2024
    Assignee: Verily Life Sciences LLC
    Inventors: Robert Wiser, Ryan Kramer, Andrew Reusch, Grant Smith
  • Publication number: 20240313771
    Abstract: In one embodiment, an electrical circuit module may include a bootstrap capacitor connected to a bootstrap-capacitor charging switch. A first signal channel may include a first sampling switch and a first control switch that controls a first connection between the bootstrap capacitor and a first control input of the first sampling switch. A second signal channel may include a second sampling switch and a second control switch that controls a second connection between the bootstrap capacitor and a second control input of the second sampling switch. The bootstrap capacitor may be charged during a first operation phase during which the bootstrap-capacitor charging switch is turned on. The first control switch of the first signal channel may be turned on during a first sub-phase of a second operation phase, and the second control switch of the second signal channel is turned on during a second sub-phase of the second operation phase.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Inventors: Umanath Ramachandra Kamath, Daniel Villamizar, Yair Shachna Shemesh, Robert Wiser, Ramakrishna Chilukuri
  • Patent number: 12073903
    Abstract: A method may be performed by a leakage monitoring and compensation system configured to estimate and compensate for leakage current in memory unit cells. The method may include identifying a leakage monitoring component associated with a memory unit cell. Further, the method may include sampling multiple leak events during a first exposure window. The method may include storing a first count representing the plurality of leak events sampled during the first exposure window. Each leak event may correspond to a unit of memory leakage. The method may include sampling multiple sensing events during a second exposure window. The method may include detecting a second count representing the sensing events sampled during the second exposure window. The method may include determining a compensation value representing a difference between the first count and the second count.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: August 27, 2024
    Assignee: Meta Platforms Technologies, LLP
    Inventors: Umanath Ramachandra Kamath, Ali Mesgarani, Robert Wiser
  • Publication number: 20240283444
    Abstract: A circuit may be configured to reduce current leakage. The circuit may include a bias generator, a charge interface, and a charge controller. The bias generator may be coupled to a first voltage source and configured to generate a first current and provide a first voltage. The charge interface may be communicatively coupled to the bias generator and configured to mirror the first current into a second current. The charge controller may be communicatively coupled to the charge interface and configured to receive the second current from the charge interface and provide a second voltage. The bias generator may be further configured to perform an ultra-low leakage switching operation in which the first voltage is switched to a third voltage while reducing a first possibility of band-band tunneling leakage at the charge interface.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Inventors: Umanath Ramachandra Kamath, Ali Mesgarani, Jason Silver, Robert Wiser, Augusto Ronchini Ximenes
  • Publication number: 20240282398
    Abstract: A method may be performed by a leakage monitoring and compensation system configured to estimate and compensate for leakage current in memory unit cells. The method may include identifying a leakage monitoring component associated with a memory unit cell. Further, the method may include sampling multiple leak events during a first exposure window. The method may include storing a first count representing the plurality of leak events sampled during the first exposure window. Each leak event may correspond to a unit of memory leakage. The method may include sampling multiple sensing events during a second exposure window. The method may include detecting a second count representing the sensing events sampled during the second exposure window. The method may include determining a compensation value representing a difference between the first count and the second count.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Umanath Ramachandra Kamath, Ali Mesgarani, Robert Wiser
  • Patent number: 12068024
    Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
    Type: Grant
    Filed: April 30, 2022
    Date of Patent: August 20, 2024
    Assignee: Ceremorphic, Inc.
    Inventors: Jay A. Chesavage, Robert Wiser, Neelam Surana
  • Publication number: 20230352082
    Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
    Type: Application
    Filed: April 30, 2022
    Publication date: November 2, 2023
    Applicant: Ceremorphic, Inc.
    Inventors: Jay A. CHESAVAGE, Robert WISER, Neelam SURANA
  • Patent number: 11699509
    Abstract: A medication dispenser apparatus is described. The apparatus includes a container configured to hold medication, a display interface, and a controller configured to perform, in sequence, a learning operation in which the controller learns a medication dispensing regimen of the container, a validation operation in which the controller validates the learned medication dispensing regimen; and a notification operation in which the controller provides on the display interface a status of use of the container for medication dispensing in relation to the learned medication dispensing regimen.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: July 11, 2023
    Assignee: Verily Life Sciences LLC
    Inventors: Robert Wiser, Ryan Kramer, Andrew Reusch, Grant Smith
  • Patent number: 11689443
    Abstract: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.
    Type: Grant
    Filed: May 29, 2021
    Date of Patent: June 27, 2023
    Assignee: Ceremorphic, Inc.
    Inventors: Robert Wiser, Venkat Mattela, Wei Xiong
  • Patent number: 11632324
    Abstract: A node mesh contains an originating node coupled to one or more nodes, each node having an communications interface input and a communications interface output. Each node has a route table with an association between a header amplitude and an output interface, such that a header having a particular amplitude causes the input node which received the message to couple the message to an associated communications interface output of the node. When the originating node outputs a message with a header amplitude, each node of the node mesh in turn directs the message to an output interface as directed by the node local route table to a terminating node of the node mesh, where the terminating node may be a training processor or inference processor for machine learning applications.
    Type: Grant
    Filed: May 29, 2021
    Date of Patent: April 18, 2023
    Assignee: Ceremorphic, Inc.
    Inventors: Robert Wiser, Venkat Mattela, Wei Xiong
  • Publication number: 20220415827
    Abstract: A plurality of integrated circuits each have a central interconnect region which is enclosed by an inner sealring, optional intermediate sealrings, and an outer sealring. Each sealring has a sealring gap for passage of a signal trace which connects a central interconnect of a first integrated circuit to a central interconnect of a second integrated circuit. In first example of the invention, the signal trace remains on a single layer and routes through sealring layer gaps between the first and second IC. In a second example of the invention, vias are used in gaps between sealrings for the signal trace to change layers such that the sealring gaps are not on the same layer. In a third example of the invention, the vias of the second example are replaced by capacitors with plates in adjacent layers.
    Type: Application
    Filed: January 31, 2022
    Publication date: December 29, 2022
    Applicant: Ceremorphic, Inc.
    Inventor: Robert Wiser
  • Publication number: 20220385565
    Abstract: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.
    Type: Application
    Filed: May 29, 2021
    Publication date: December 1, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Robert WISER, Venkat MATTELA, Wei XIONG
  • Publication number: 20220385566
    Abstract: A node mesh contains an originating node coupled to one or more nodes, each node having an communications interface input and a communications interface output. Each node has a route table with an association between a header amplitude and an output interface, such that a header having a particular amplitude causes the input node which received the message to couple the message to an associated communications interface output of the node. When the originating node outputs a message with a header amplitude, each node of the node mesh in turn directs the message to an output interface as directed by the node local route table to a terminating node of the node mesh, where the terminating node may be a training processor or inference processor for machine learning applications.
    Type: Application
    Filed: May 29, 2021
    Publication date: December 1, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Robert WISER, Venkat MATTELA, Wei XIONG
  • Patent number: 11272454
    Abstract: One illustrative example includes wireless device having a first wake-up receiver and a second wake-up receiver. The first wake-up receiver can detect a first wake-up signal within a first group of wireless signals and responsively activate the second wake-up receiver. The second wake-up receiver can then detect a second wake-up signal within a second group of wireless signals and responsively activate a transceiver, where the transceiver is usable to engage in bidirectional communication with a remote device.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 8, 2022
    Assignee: VERILY LIFE SCIENCES LLC
    Inventors: Tong Zhang, Grant Anderson, Grant Smith, Robert Wiser
  • Patent number: 11171625
    Abstract: Examples of increasing yield and operating temperature range of transmitters are disclosed. In one example, a transmitter has an a thin-film bulk acoustic (FBAR) resonator. The transmitter may be a Bluetooth Low Energy (BLE) transmitter. In this example, the FBAR-based BLE transmitter does not require or have a phase locked loop, and does not require or have a crystal reference. The FBAR-based BLE transmitter may have an oscillator with a split capacitor array. The oscillator may be a Pierce oscillator with a split capacitor array. The FBAR-based transmitter and calibration methods described herein provide a greater yield and wider operating range than prior transmitters.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 9, 2021
    Assignee: VERILY LIFE SCIENCES LLC
    Inventors: Kannan Sankaragomathi, Justin Schauer, Robert Wiser, Daniel Yeager
  • Patent number: 11033461
    Abstract: Systems and methods for monitoring medication adherence and compliance are provided. A medication monitoring system may include a medication container, a cover, and a beacon system. The beacon system may include a beacon that transmits a wireless signal when the cover is removed from the medication container. A method for monitoring medication adherence and compliance may include detecting when a cover of a medication container is removed from the medication container. The method may further include transmitting based on the detection, a signal from a beacon to a remote device, which indicates the opening of the medication container.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: June 15, 2021
    Assignee: VERILY LIFE SCIENCES LLC
    Inventors: Robert Wiser, Daniel Barrows, Jeremy Emken
  • Patent number: 10937533
    Abstract: A medication dispenser apparatus is described. The apparatus includes a container configured to hold medication, a display interface, and a controller configured to perform, in sequence, a learning operation in which the controller learns a medication dispensing regimen of the container, a validation operation in which the controller validates the learned medication dispensing regimen; and a notification operation in which the controller provides on the display interface a status of use of the container for medication dispensing in relation to the learned medication dispensing regimen.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 2, 2021
    Assignee: Verily Life Sciences LLC
    Inventors: Robert Wiser, Ryan Kramer, Andrew Reusch, Grant Smith
  • Patent number: 10606560
    Abstract: Deterministic asymmetry in a random number generator can be mitigated by a circuit that includes a first inverter, a second inverter, a first capacitor, a second capacitor, a first switch, and a second switch. The first inverter can include a first input terminal and a first output terminal. The first inverter can have a first inverter threshold voltage. The second inverter can include a second input terminal and a second output terminal. The second inverter can have a second inverter threshold voltage. The first capacitor can be conductively coupled between the first output terminal and the second output terminal. The second capacitor can be conductively coupled between the second output terminal and the first input terminal. The first switch can be conductively coupled between the first input terminal and the first output terminal. The second switch can be conductively coupled between the second input terminal and the second output terminal.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 31, 2020
    Assignee: VERILY LIFE SCIENCES LLC
    Inventors: Nathan Pletcher, Robert Wiser, Alireza Dastgheib
  • Patent number: 10554198
    Abstract: A clock calibration system is described herein. The clock calibration system may be implemented in a medical device to control timing of an action performed by the medical device. The clock calibration system may include a processing device coupled to a clock oscillator and a reference oscillator.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 4, 2020
    Assignee: VERILY LIFE SERVICES LLC
    Inventors: Amirpouya Kavousian, Robert Wiser