Patents by Inventor Robert Wisnieff
Robert Wisnieff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9941788Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: GrantFiled: May 2, 2017Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Publication number: 20170237344Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: ApplicationFiled: May 2, 2017Publication date: August 17, 2017Inventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Patent number: 9660525Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: GrantFiled: December 1, 2016Date of Patent: May 23, 2017Assignee: International Business Machines CorporationInventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Publication number: 20170085173Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: ApplicationFiled: December 1, 2016Publication date: March 23, 2017Inventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Patent number: 9520779Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: GrantFiled: March 17, 2016Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Publication number: 20160254744Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: ApplicationFiled: March 17, 2016Publication date: September 1, 2016Inventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Patent number: 9312761Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: GrantFiled: February 12, 2014Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Publication number: 20150229295Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.Type: ApplicationFiled: February 12, 2014Publication date: August 13, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
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Patent number: 7811923Abstract: The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material.Type: GrantFiled: July 17, 2007Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Sampath Purushothaman, Robert Wisnieff
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Publication number: 20090023284Abstract: The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material.Type: ApplicationFiled: July 17, 2007Publication date: January 22, 2009Applicant: IBM Corporation (Yorktown)Inventors: Qinghuang Lin, Sampath Purushothaman, Robert Wisnieff
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Publication number: 20080066860Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.Type: ApplicationFiled: October 12, 2007Publication date: March 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Cotte, Nils Hoivik, Christopher Jahnes, Robert Wisnieff
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Publication number: 20080067683Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.Type: ApplicationFiled: October 12, 2007Publication date: March 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Cotte, Nils Hoivik, Christopher Jahnes, Robert Wisnieff
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Publication number: 20070290233Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: ApplicationFiled: August 23, 2007Publication date: December 20, 2007Inventors: Geoffrey Burr, Chandrasekharan Kothandaraman, Chung Hon Lam, Xiao Hu Liu, Stephen Rossnagel, Christy Tyberg, Robert Wisnieff
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Publication number: 20070194450Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: February 21, 2006Publication date: August 23, 2007Inventors: Christy Tyberg, Katherine Saenger, Jack Chu, Harold Hovel, Robert Wisnieff, Kerry Bernstein, Stephen Bedell
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Publication number: 20070045844Abstract: A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.Type: ApplicationFiled: August 24, 2005Publication date: March 1, 2007Inventors: Paul Andry, Cyril Cabral, Kenneth Rodbell, Robert Wisnieff
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Publication number: 20060278895Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.Type: ApplicationFiled: June 14, 2005Publication date: December 14, 2006Inventors: Geoffrey Burr, Chandrasekharan Kothandaraman, Chung Lam, Xiao Liu, Stephen Rossnagel, Christy Tyberg, Robert Wisnieff
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Publication number: 20060220152Abstract: Disclosed is a MOSFET structure and method of fabricating the structure that incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. In one embodiment, the multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. In another embodiment, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. Either embodiment may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Applicant: International Business Machines CorporationInventors: Elbert Huang, Philip Oldiges, Ghavam Shahidi, Christy Tyberg, Xinlin Wang, Robert Wisnieff
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Publication number: 20060189134Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Applicant: International Business Machines CorporationInventors: John Cotte, Nils Hoivik, Christopher Jahnes, Robert Wisnieff
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Publication number: 20050045889Abstract: The present invention is directed to a thin film transistor (and related multilayer structures) that includes: source and drain electrodes 14 and 15 disposed at a specified interval above an insulating substrate 11 and formed by printing-and-plating; an a-Si film 16 disposed for the source and drain electrodes 14 and 15; a gate insulating film 17 laminated on the a-Si film 16; and a gate electrode 18 laminated on the gate insulating film 17 and formed by printing-and-plating. The a-Si film 16 and the gate insulating film 17 have an offset region 20 that uniformly extends beyond the dimensions of the gate electrode 18.Type: ApplicationFiled: July 14, 2004Publication date: March 3, 2005Applicant: International Business Machines CorporationInventors: Peter Fryer, Robert Wisnieff, Takatoshi Tsujimura