Abstract: A system and method for collecting and displaying time sensitive information consisting of multiple information sources connected to an information storage facility via an upload link. The information storage facility may, in turn, be interrogated by information sinks via a download link to display the collected time sensitive information. The system may support multiple alternate information storage facilities by allowing them to connect to the information storage facility via an API. The multiple alternate information storage facilities may communicate with information sinks via an alternate download link.

Abstract: I describe and claim a multiple audio signal presentation system and method. The multiple audio signal presentation system includes a presentation system to present a plurality of audio signals, and a controller to manipulate one or more of the audio signals, where the audio signals, when concurrently presented by the presentation system, are audibly differentiable responsive to the manipulation.

Abstract: We describe and claim television channel change picture-in-picture circuit and method. The circuit includes means for displaying a first channel on a primary portion of a screen, means for changing from the first channel to a second channel, and means for displaying the second channel on a secondary portion of the screen responsive to the means for changing from the first to the second channel while continuing to display the first channel on the primary portion of the screen.

Abstract: An embodiment may include a method to convert a video signal with an analog to digital converter in a video decoder, convert an audio signal with the analog to digital converter, demodulate the audio signal with an audio demodulator and amplify the audio signal with a programmable gain amplifier before it is converted in the analog to digital converter. In an embodiment the programmable gain amplifier may receive a control signal from the audio demodulator to adjust the audio signal level. Another embodiment may provide a video decoder comprising a programmable gain controller, an analog to digital converter coupled with the programmable gain controller, the converter to digitize audio and video information, and an audio demodulator coupled with the analog to digital converter, the audio demodulator to control the programmable gain controller for an audio signal.

Abstract: We describe a cropped and scaled picture-in-picture system and method. The video system includes a first video port to generate a first video signal portion from a first video signal, a second video port to generate a second video signal portion from a second video signal, and a video processor to generate a composite image from the first and second video signal portions.

Abstract: We describe and claim television channel change picture-in-picture circuit and method. The circuit includes means for displaying a first channel on a primary portion of a screen, means for changing from the first channel to a second channel, and means for displaying the second channel on a secondary portion of the screen responsive to the means for changing from the first to the second channel while continuing to display the first channel on the primary portion of the screen.

Abstract: We describe and claim a film mode judder elimination circuit and method. A film mode detector detects a film mode in a video signal. A judder eliminator eliminates judder by dynamically transitioning from one field rate, e.g., 60 Hz, to another field rate, e.g., 48 Hz or 72 Hz, responsive to the detection. The transition between the one and another field rate may occur during the vertical blanking period to avoid flicker.

Abstract: The invention relates to a multiplexed video digitization system and method. The system includes a plurality of analog video signals, a multiplexer to select one of the plurality of analog video signals, and an analog-to-digital converter to convert the selected analog video signal into a digital video signal. The plurality of analog video signals may include component video signals, red, green, and blue signals, or s-video signals. The multiplexer may include control logic to select the one of the plurality of analog video signals. The system may include a plurality of sample and hold circuits to insure time aligned sampling of the corresponding plurality of video signals.

Abstract: The invention is a circuit and method for automatically adjusting the phase and frequency of a pixel clock derived from analog image data. The circuit includes a phase locked loop circuit adapted to generate a phase locked loop clock responsive to a reference signal and an edge detector circuit adapted to generate an edge pulse signal corresponding to a transition of an analog data signal. A phase detector circuit is adapted to identify a phase of the phase locked loop clock associated to the transition of the analog data and thereby generate a phase adjust signal. A phase adjust circuit is adapted to generate a pixel clock by adjusting the phase of the phase locked loop clock responsive to the phase adjust signal.

Abstract: The invention describes a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input vertical refresh rate and displays the image data at a vertical refresh rate that is a predetermined fraction of the input vertical refresh rate.

Abstract: The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

Abstract: The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

Abstract: A heel brake integrated with a skate truck for a roller skate shoe is formed integrally with a skate truck body portion from which axles laterally project. A brake knob made of rubber is attached to the distal end of the brake. Thus, the brake is formed as a part of the truck and not as a part of the skate chassis. A combined skate shoe and wheel truck assembly is likewise formed integrally, optionally comprising braking means, an axle, and a wheel.

Abstract: An image scaling circuit for increasing or decreasing the size of a sampled image to match a fixed resolution display. The circuit includes means for resizing the image in the horizontal and vertical dimension using independent sample rate converters. The sample rate converters increase or decrease the image size by a factor of Lx/Mx in the horizontal dimension and Ly/My in the vertical dimension where Lx and Ly are integers and Mx and My are decimal numbers of arbitrary precision to provide fine scaling control. In addition, image warping is conveniently implemented by varying the down sample ratios Mx and My on a pixel by pixel and/or line by line basis.