Abstract: An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Abstract: Generally, the present invention utilizes dry plasma etching techniques such as Electron Cyclotron Resonance (ECR) to produce sloped sidewalls on a DRAM storage cell. The rounded corners of the lower electrode made by this technique allow the advanced dielectric material to be deposited without substantial cracking, and it also allows the capacitance to be closely predicted and controlled due to the uniformity in which the advanced dielectric layer can be fabricated. One embodiment of the present invention is method of making a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises a barrier layer (e.g. TiN 36), and an unreactive layer (e.g. Pt 42).