Patents by Inventor Robert Y S Huang

Robert Y S Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mask layer and dual damascene interconnect structure in a semiconductor device
    Patent number: 7067419
    Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: June 27, 2006
    Assignee: Agere Systems, Inc.
    Inventors: Robert Y S Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt George Steiner, Joseph Ashley Taylor
  • Method and apparatus using an on-chip ring oscillator for chip identification
    Patent number: 6893883
    Abstract: An apparatus and method for identifying integrated circuit chips or dice on a semiconductor wafer. Each chip comprises a ring oscillator having a characteristic oscillating frequency different from the oscillating frequency of the ring oscillators of other chips on the same wafer. Each chip can be associated with various attributes of the wafer on which it was formed and the process steps to which it was subjected using the ring oscillator frequency.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: May 17, 2005
    Assignee: Agere Systems Inc.
    Inventors: Frank Yauchee Hui, Robert Y S Huang
  • Mask layer and dual damascene interconnect structure in a semiconductor device
    Publication number: 20030119305
    Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Robert Y. S. Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt Geroge Steiner, Joseph Ashley Taylor
  • Process for improving device yield in integrated circuit fabrication
    Patent number: 5950096
    Abstract: In the fabrication of an integrated circuit, undesirable bird's beak pull back due to damage caused during ion implantation is alleviated by means of rapid thermal annealing step prior to chemical etching.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: September 7, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Robert Y.S. Huang, David Kou-Fong Hwang, Stephen Carl Kuehne, Jean Ling Lee, Jane Qian Liu, Yi Ma, Minseok Oh
  • Drain extension regions in low voltage lateral DMOS devices
    Patent number: 5846866
    Abstract: Disclosed are MOSFET devices in which a region extends from the drain and is, self-aligned with the gate. The region has a lower dopant concentration than the drain. The presence of the extension region substantially enhances breakdown voltage while not adding excessive on-resistance for the devices.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: December 8, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Robert Y. S. Huang, Monir El-Diwany